Memory system

ABSTRACT

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/052,238, filed on Aug. 1, 2018, which is based upon and claims thebenefit of priority from Japanese Patent Application No. 2017-172150,filed Sep. 7, 2017, the entire contents of which are incorporated hereinby reference.

FIELD

Embodiments described herein relate generally to a memory system.

BACKGROUND

A NAND-type flash memory is known in which memory cells are stacked inthree dimensions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example constitution of a memorysystem according to a first embodiment;

FIG. 2 is a block diagram showing an example constitution of a NAND-typeflash memory according to the first embodiment;

FIG. 3 is a circuit diagram showing an example constitution of a memorycell array contained in the NAND-type flash memory according to thefirst embodiment;

FIG. 4 is a diagram showing an example of threshold voltage distributionof memory cell transistors contained in the NAND-type flash memory andread voltages for each state according to the first embodiment;

FIG. 5 is a sectional view showing an example of a structure of thememory cell array contained in the NAND-type flash memory according tothe first embodiment;

FIG. 6 is a block diagram showing a detailed example constitution of aprocessor contained in a memory controller according to the firstembodiment;

FIG. 7 is a flow chart showing an example of a patrol operation in amemory system according to the first embodiment;

FIG. 8 is a diagram showing an example of transition of a patrolprocessing rate in a patrol period of the memory system according to thefirst embodiment;

FIG. 9 is a diagram showing an example of each of a command sequence anda waveform of a first dummy read in the memory system according to thefirst embodiment;

FIG. 10 is a diagram showing an example of each of a command sequenceand a waveform of a second dummy read in the memory system according tothe first embodiment;

FIG. 11 is a diagram showing an example of a selection criterion of adummy read process in the patrol period of the memory system accordingto the first embodiment;

FIG. 12 is a waveform chart showing an example of a creep up phenomenonwhich occurs after a read operation of the NAND-type flash memory;

FIG. 13 is a block diagram showing a detailed example constitution of aprocessor contained in a memory controller according to a secondembodiment;

FIG. 14 is a flow chart showing an example of the patrol operation inthe memory system according to the second embodiment;

FIG. 15 is a diagram showing an example of transition of the number ofpatrolled blocks in a patrol period of the memory system according tothe second embodiment;

FIG. 16 is a flow chart showing a modified example of the patroloperation in the memory system according to the second embodiment;

FIG. 17 is a block diagram showing a detailed example constitution of aprocessor contained in a memory controller according to a thirdembodiment;

FIG. 18 is a flow chart showing an example of a patrol operation in amemory system according to the third embodiment;

FIG. 19 is a diagram showing an example of transition of a patrolprocessing rate in a patrol period of the memory system according to thethird embodiment;

FIG. 20 is a block diagram showing a detailed example constitution of amemory system according to a fourth embodiment;

FIG. 21 is a table showing an example of attribute information of eachof blocks in a memory system according to the fourth embodiment;

FIG. 22 is a diagram showing an example of a processing order for dummyread based on a priority in a patrol operation of each of a first patrolperiod and a second patrol period of the memory system according to thefourth embodiment;

FIG. 23 is a diagram showing an example of a processing order for dummyread based on a priority in a patrol operation of a patrol period of thememory system according to the fourth embodiment;

FIG. 24 is a circuit diagram showing a detailed example constitution ofa row decoder module and a voltage generator contained in a NAND-typeflash memory according to a fifth embodiment;

FIG. 25 is a flow chart showing an example of a patrol operation in amemory system according to the fifth embodiment;

FIG. 26 is a diagram showing an example of a managing method of aPATROLLED flag in the patrol operation of the memory system according tothe fifth embodiment;

FIG. 27 is a diagram showing an example of each of a command sequenceand a waveform of a first dummy read in the memory system according tothe fifth embodiment;

FIG. 28 is a diagram showing an example of each of a command sequenceand a waveform of a second dummy read in the memory system according tothe fifth embodiment;

FIG. 29 is a flow chart showing an example of a patrol operation in amemory system according to a modified example of the fifth embodiment;

FIG. 30 is a block diagram showing detailed example constitution of amemory system and a host apparatus in a sixth embodiment;

FIG. 31 is a table showing an example of a relation between partitionIDs and physical block addresses in a memory system according to thesixth embodiment;

FIG. 32 is a flow chart showing an example of a patrol operation in thememory system according to the sixth embodiment;

FIG. 33 is a table showing a relation between an installation example ofpartitions and power consumption during a second dummy read in thememory system according to the sixth embodiment;

FIG. 34 is a block diagram showing detailed example constitution of amemory system and a host apparatus in a seventh embodiment;

FIG. 35 is a flow chart showing an example of a patrol operation in thememory system according to the seventh embodiment;

FIG. 36 is a table showing an example of first priority information inthe memory system according to the seventh embodiment;

FIG. 37 is a table showing an example of second priority information inthe memory system according to the seventh embodiment;

FIG. 38 is a table showing an example of priority setting based onpriority information shown in FIG. 34;

FIG. 39 is a table showing an example of priority setting based onpriority information shown in FIG. 35;

FIG. 40 is a table showing an example of dummy read setting based onpriority information in the memory system according to the seventhembodiment; and

FIG. 41 is a diagram showing an example of a command sequence which isused for setting modification of a NAND-type flash memory in each of thefirst through seventh embodiments.

DETAILED DESCRIPTION

A memory system of an embodiment includes a semiconductor memory and acontroller. The semiconductor memory includes blocks each containingmemory cells. The controller is configured to instruct the semiconductormemory to execute a first operation and a second operation. In the firstoperation and the second operation, the semiconductor memory selects atleast one of the blocks, and applies at least one voltage to all memorycells contained in said selected blocks. A number of blocks to whichsaid voltage is applied per unit time in the second operation is largerthan that in the first operation.

Hereinafter, description will be made as to embodiments with referenceto the drawings. The drawings are schematic, and the relationshipbetween a thickness and a planar dimension, the ratio betweenthicknesses of the respective layers, or the like are different fromthose in actual cases. It is to be noted that in the followingdescription, constitutional elements having about the same function andconstitution are denoted with the same reference sign, and redundantdescription is avoided. A numeral after a character constituting thereference sign and a character after a numeral constituting thereference sign are referred to with the reference sign including thesame character and numeral, and are used in distinguishing elementshaving similar constitutions from each other. When the elements denotedwith the reference signs including the same character or numeral do nothave to be distinguished from each other, these elements are referred towith the reference sign only including the same character or the samenumeral.

[1] First Embodiment

Hereinafter, description will be made as to a memory system according toa first embodiment.

[1-1] Constitution

[1-1-1] Constitution of Memory System 1

FIG. 1 is a block diagram showing an example constitution of a memorysystem 1 according to the first embodiment. As shown in FIG. 1, thememory system 1 comprises NAND-type flash memory chips 10A and 10B, aDRAM (dynamic random access memory) 3, and a memory controller 20.

The NAND-type flash memory chips 10A and 10B are nonvolatile memorywhich are capable of storing data in non-volatile manner. The NAND-typeflash memory chips 10A and 10B may operate independently of each other.It is to be noted that the number of NAND-type flash memory chips 10 ofthe memory system 1 is not limited to that in this example, and anynumber may be applied.

The DRAM 3 is a volatile memory which is capable of temporarily storingthe data. It is to be noted that the number of the volatile memory chipsof the memory system 1 is not limited to that in this example, and anynumber may be applied. Furthermore, a type of an volatile memory of thememory system 1 is not limited to the DRAM. For example, the memorysystem 1 may comprise an SRAM (static random access memory) or the likeas the volatile memory.

The memory controller 20 is an IC (integrated circuit) such as SoC(System-on-a-chip), FPGA (Field programmable gate array) or ASIC(Application specific integrated circuit), and may instruct theNAND-type flash memory 10 and the DRAM 3 to execute various operations.Furthermore, the memory controller 20 may execute an operation based ona command from an external host apparatus 2 and an operationirrespective of the command from the host apparatus 2. Description willbe made later as to a constitution of the memory controller 20.

[1-1-2] Constitution of NAND-Type Flash Memory 10

FIG. 2 is a block diagram showing an example constitution of theNAND-type flash memory 10 according to the first embodiment. As shown inFIG. 2, the NAND-type flash memory 10 comprises a memory cell array 11,a sense amplifier module 12, a row decoder module 13, an input/outputcircuit 14, a register 15, a logic controller 16, a sequencer 17, aready/busy controller 18, and a voltage generator 19.

The memory cell array 11 includes blocks BLK0 through BLKn (n is aninteger of 0 or more). A block BLK is a set of nonvolatile memory cellsassociated with bit lines and word lines, and is, for example, an eraseunit of data. For example, a multi-level cell (MLC) mode is applied tothe NAND-type flash memory 10, whereby data of 2 bit or more may bestored in each memory cell.

The sense amplifier module 12 may output data DAT read from the memorycell array 11 to the memory controller 20 via the input/output circuit14. Furthermore, the sense amplifier module 12 may transfer, to thememory cell array 11, the data to be written DAT received from thememory controller 20 via the input/output circuit 14.

The row decoder module 13 may select a block BLK of a target of variousoperations, on the basis of a block address held in an address register15B. In addition, the row decoder module 13 may transfer, to theselected block BLK, a voltage supplied from the voltage generator 19.

For example, input/output signals I/O with 8-bit width (I/O1 throughI/O8) may be transmitted and received between the input/output circuit14 and the memory controller 20. For example, the input/output circuit14 transfers, to the sense amplifier module 12, the data to be writtenDAT included in the input/output signal I/O received from the memorycontroller 20, and transmits the read data DAT transferred from thesense amplifier module 12, as the input/output signal I/O to the memorycontroller 20.

The register 15 includes a status register 15A, the address register15B, and a command register 15C. The status register 15A holds, forexample, status information STS of the sequencer 17 and transfers thisstatus information STS to the input/output circuit 14 on the basis of aninstruction of the sequencer 17. The address register 15B holds addressinformation ADD transferred from the input/output circuit 14. Forexample, column addresses and block addresses included in the addressinformation ADD are used in the sense amplifier module 12 and the rowdecoder module 13, respectively. The command register 15C holds acommand CMD transferred from the input/output circuit 14.

The logic controller 16 may control the input/output circuit 14 and thesequencer 17 on the basis of various control signals received from thememory controller 20. As the various control signals, there are used,for example, a chip enable signal /CE, a command latch enable signalCLE, an address latch enable signal ALE, a write enable signal /WE, aread enable signal /RE, and a write protect signal /WP. The signal /CEis a signal to enable the NAND-type flash memory 10 to operate. Thesignal CLE is a signal to notify the input/output circuit 14 that asignal to be input into the NAND-type flash memory 10 is a command CMD.The signal ALE is a signal to notify the input/output circuit 14 that asignal to be input into the NAND-type flash memory 10 is the addressinformation ADD. Each of the signals /WE and /RE is, for example, asignal to instruct the input/output circuit 14 to execute input andoutput of the input/output signal I/O. The signal /WP is, for example, asignal to adjust the NAND-type flash memory 10 in a protective statewhen a power source turns on or off.

The sequencer 17 may control an operation of the whole NAND-type flashmemory 10 on the basis of the command CMD held in the command register15C. For example, the sequencer 17 controls the sense amplifier module12, the row decoder module 13, the voltage generator 19 and the like toexecute various operations such as a write operation and a readoperation.

The ready/busy controller 18 may generate a ready/busy signal RBn on thebasis of an operation state of the sequencer 17. The signal RBn is asignal to notify the memory controller 20 whether the NAND-type flashmemory 10 is in a ready state to receive the command from the memorycontroller 20 or in a busy state where the memory does not receive thecommand.

The voltage generator 19 may generate an appropriate voltage on thebasis of control of the sequencer 17, and may supply the generatedvoltage to a selected portion of the memory cell array 11, the senseamplifier module 12, the row decoder module 13 or the like. For example,the voltage generator 19 applies the appropriate voltage to each of asignal line corresponding to the selected word line and a signal linecorresponding to a non-selected word line on the basis of a page addressheld in the address register 15B.

[1-1-3] Constitution of Memory Cell Array 11

FIG. 3 is a circuit diagram showing an example constitution of thememory cell array 11 contained in the NAND-type flash memory 10according to the first embodiment, and shows a detailed circuitconstitution of a block BLK in the memory cell array 11. As shown inFIG. 3, the block BLK includes, for example, four string units SU0through SU3.

Each string unit SU includes NAND strings NSs which are associated withbit lines BL0 through BLm (m is an integer of 0 or more), respectively.Each NAND string NS includes, for example, memory cell transistors MT0through MT7 and selection transistors ST1 and ST2.

A memory cell transistor MT comprises a control gate and a chargestorage layer, and may store data in non-volatile manner. The memorycell transistors MT0 through MT7 contained in each NAND string NS areconnected in series between a source of the selection transistor ST1 anda drain of the selection transistor ST2. Control gates of memory celltransistors MT (MT0 through MT7) aligned in a same word line WL withdifferent bit lines are connected to common word line WL (WL0 throughWL7, respectively). It is to be noted that in the following description,a group of memory cell transistors MTs connected to the common word lineWL in each string unit SU in a block BLK is referred to as a “cell unitCU”. In a case where 1-bit data is stored in each memory cell transistorMT, a set of 1-bit data to be or being stored in a cell unit CU isreferred to as a “page”. In a case where 2-bit data is stored in amemory cell transistor MT, a cell unit CU stores 2-page data.

The selection transistors ST1 and ST2 are used to select a string unitSU during various operations. A drain of the selection transistor ST1contained in the NAND string NS corresponding to the same column addressis connected to its corresponding common bit line BL. Gates of theselection transistors ST1 contained in the string units SU0 through SU3are connected to common selection gate lines SGD0 through SGD3,respectively. In the same block BLK, a source of the selectiontransistor ST2 is connected to a common source line SL, and a gate ofthe selection transistor ST2 is connected to a common selection gateline SGS.

In the above-mentioned circuit constitution of the memory cell array 11,the word lines WL0 through WL7 are disposed every block BLK. The bitlines BL0 through BLm are shared among the blocks BLKs. The source lineSL is shared among the blocks BLKs. It is to be noted that the number ofthe string units SUs contained in each block BLK and the numbers of thememory cell transistors MTs and the selection transistors ST1 and ST2contained in each NAND string NS are merely examples, and any number maybe applied. The numbers of the word lines WLs and the selection gatelines SGD and SGS are altered on the basis of the numbers of the memorycell transistors MTs and the selection transistors ST1 and ST2.

Furthermore, in the above-mentioned circuit constitution of the memorycell array 11, a threshold voltage distribution is formed by thresholdvoltages of a cell unit CU, for example, as shown in FIG. 4. FIG. 4shows threshold voltage distribution of the memory cell transistors MTsand read voltages for each state, in a case where each memory celltransistor MT stores 1-bit data or 2-bit data, each ordinate indicatesthe number of the memory cell transistors MTs, and each abscissaindicates a threshold voltage Vth of the memory cell transistor MT. Asshown in FIG. 4, the memory cell transistors MTs form threshold voltagedistribution on the basis of a number of bits of data stored in a memorycell transistor MT. Hereinafter, description will be made as to each ofa single-level cell (SLC) mode in which the 1-bit data is stored in onememory cell transistor MT and a multi-level cell (MLC) mode in which the2-bit or more data is stored in one memory cell transistor MT, as anexample of a write mode.

In the SLC mode, the memory cell transistors MTs form two lobes ofthreshold voltage distribution. These two lobes of threshold voltagedistribution are referred to as an “ER”-state and an “A”-state in orderof threshold voltage from lower to higher. In the SLC mode, for example,“1” data and “0” data are assigned to the “ER”-state and the “A”-state,respectively.

In the MLC mode, the memory cell transistors MTs form four lobes ofthreshold voltage distribution. These four lobes are referred to as an“ER”-state, an “A”-state, a “B”-state and a “C”-state in order ofthreshold voltage from lower to higher.

In the MLC mode, for example, “11 (upper/lower)” data, “01” data, “00”data and “10” data are assigned to the “ER”-state, the “A”-state, the“B”-state and the “C”-state, respectively.

Then, in the above-mentioned threshold voltage distribution, each readvoltage is set between the lobes of threshold voltage distributionadjacent to each other. For example, a read voltage AR is set between ahighest threshold voltage in the “ER”-state and a lowest thresholdvoltage in the “A”-state, and this read voltage is for use in anoperation of judging whether the threshold voltage of the memory celltransistor MT is included in the lobe of threshold voltage distributionof the “ER”-state or in the lobe of threshold voltage distribution ofthe “A”-state or states with higher threshold voltage. When the readvoltage AR is applied to the memory cell transistors MTs, the memorycell transistors corresponding to the “ER”-state are turned on, and thememory cell transistors corresponding to the “A”-state, the “B”-stateand the “C”-state are turned off. The other read voltages are alsosimilarly set, a read voltage BR is set between the lobe of thresholdvoltage distribution of the “A”-state and the lobe of threshold voltagedistribution of the “B”-state, and a read voltage CR is set between thelobe of threshold voltage distribution of the “B”-state and the lobe ofthreshold voltage distribution of the “C”-state. When the read voltageBR is applied to the memory cell transistors MTs, the memory celltransistors corresponding to the “ER”-state and the “A”-state are turnedon, and the memory cell transistors corresponding to the “B”-state andthe “C”-state are turned off. When the read voltage CR is applied to thememory cell transistors MTs, the memory cell transistors correspondingto the “ER”-state, the “A”-state and the “B”-state are turned on, andthe memory cell transistors corresponding to the “C”-state are turnedoff. In each write mode, a read pass voltage VREAD is set to a voltagehigher than the highest threshold voltage in the lobe with highestthreshold voltage. Specifically, when the read pass voltage VREAD isapplied to the gate of the memory cell transistor MT, the memory celltransistor turns on irrespective of the data being stored.

It is to be noted that the number of bits of data being or to be storedin one memory cell transistor MT and the assignment of the data (i.e.,encoding) to the states of threshold voltage in the memory celltransistor MT described above are merely examples, and the presentinvention is not limited to this example. For example, the data of 3bits or more may be stored in a memory cell transistor MT, and othervarious assignments of the data may be applied to the lobes of thresholdvoltage distribution. Furthermore, each of the read voltages and theread pass voltage may be changed or not changed, depending on the writemodes.

For example, as shown in FIG. 4, the read pass voltage VREAD in the MLCmode may be set to be higher than the read pass voltage VREAD in the SLCmode. Similarly, for example, a read pass voltage VREAD in atriple-level cell (TLC) mode in which 3-bit data is stored in one memorycell transistor MT may be set to be higher than the read pass voltageVREAD in the MLC mode, and a read pass voltage VREAD in aquadruple-level cell (QLC) mode in which 4-bit data is stored in onememory cell transistor MT may be set to be higher than the read passvoltage VREAD in the TLC mode.

Next, description will be made as to a sectional structure of the memorycell array 11 with reference to FIG. 5. FIG. 5 is a sectional viewshowing an example of the structure of the memory cell array 11contained in the NAND-type flash memory 10 according to the firstembodiment, and shows a cross section of the memory cell array 11 inwhich showing an interlayer insulator film is omitted, and an X-axis, aY-axis and a Z-axis. As shown in FIG. 5, the NAND-type flash memory 10comprises a p-type well region 30, conductors 31 through 36,semiconductor pillars MHs, and contact plugs LIs.

The p-type well region 30 is formed in the surface area of asemiconductor substrate. On the p-type well region 30, for example, theconductors 31 of four layers, the conductors 32 of eight layers and theconductors 33 of four layers are stacked in order with the interlayerinsulator films. Each of the conductors 31 through 33 is disposed, forexample, in the form of a plate which spreads in the X-direction and theY-direction. The conductors 31 and 33 function as the selection gatelines SGS and SGD, respectively, and the conductor 32 functions as theword line WL. Each of stacked conductors 32 is assigned to one word lineWL. For each of the selection gate lines SGS and SGD, either of theconductor disposed in one layer or the conductors stacked in multiplelayers as shown in FIG. 5 may be assigned.

The semiconductor pillars MHs are formed to extend from an upper surfaceof the conductor 33 to an upper surface of the p-type well region 30.That is, the semiconductor pillars MHs are disposed to pass theconductors 31 through 33 along the Z-direction. Each semiconductorpillar MH includes a block insulator film 37, an insulator film (acharge storage layer) 38, a tunnel oxide film 39, and a semiconductormaterial 40. The semiconductor material 40 includes a conductivematerial and is formed in a pillar shape. Then, the tunnel oxide film39, the insulator film 38 and the block insulator film 37 are formed inorder, to cover a side surface of the semiconductor material 40.

The conductor 34 is formed in a layer above the conductor 33 and thesemiconductor pillar MH. The conductor 34 functions as the bit line BLand is connected to the corresponding semiconductor pillar MH. It is tobe noted that a contact plug made of a conductive material may be formedbetween the conductor 34 and the semiconductor pillar MH.

The conductors 35 and 36 are formed in a wire layer between theconductor 33 and the conductor 34. The conductor 35 functions as thesource line SL, and is connected to an n+-type impurity diffusion region41 formed in the surface of the well region 30 via the contact plug LI.The conductor 36 functions as a well line CPWELL, and is connected to ap+-type impurity diffusion region 42 formed in the surface of the wellregion 30 via the contact plug LI. Each contact plug LI is disposed inthe form of a plate which spreads, for example, in the X-direction andthe Z-direction.

In the above-mentioned structure of the memory cell array 11, onesemiconductor pillar MH corresponds to one NAND string NS. Specifically,an intersection point of the conductor 31 and the semiconductor pillarMH corresponds to the selection transistor ST2, an intersection point ofthe conductor 32 and the semiconductor pillar MH corresponds to the wordline WL, and an intersection point of the conductor 33 and thesemiconductor pillar MH corresponds to the selection transistor ST1. Theconductor 31 of the lowermost layer and the tunnel oxide film 39 aredisposed in the vicinity of the n+-type impurity diffusion region 41,and hence, when the selection transistor ST2 is turned on, a currentpath is formed between the NAND string NS and the n+-type impuritydiffusion region 41.

Furthermore, the above-mentioned structures of the memory cell arrays 11are arranged in the X-direction. For example, one string unit SU isconstituted of a set of NAND strings NSs arranged in the X-direction.Additionally, in a case where the string units SUs are arranged in thesame block BLK, the conductor 33 corresponding to the selection gateline SGD is separated between the string units SUs.

It is to be noted that a way to constitute the memory cell allay 11 maybe employed other than the above-mentioned constitution. Otherconstitutions of the memory cell array 11 are described in U.S. patentapplication Ser. No. 12/407,403 entitled “Three Dimensional StackedNonvolatile Semiconductor Memory” filed on Mar. 19, 2009, U.S. patentapplication Ser. No. 12/406,524 entitled “Three Dimensional StackedNonvolatile Semiconductor Memory” filed on Mar. 18, 2009, U.S. patentapplication Ser. No. 12/679,991 entitled “Nonvolatile SemiconductorStorage Device and Manufacturing Method of the Same” filed on Mar. 25,2010, and U.S. patent application Ser. No. 12/532,030 entitled“Semiconductor Memory and Manufacturing Method of the Same” filed onMar. 23, 2009. These patent applications are incorporated by referenceherein in their entireties.

[1-1-4] Constitution of Memory Controller 20

Here, turning back to FIG. 1, description is made as to a constitutionof the memory controller 20. As shown in FIG. 1, the memory controller20 comprises a processor (CPU: central processing unit) 21, an internalmemory (RAM: random access memory) 22, a host interface circuit 23, atimer 24, a thermometer 25, a NAND interface circuit 26, and a DRAMinterface circuit 27.

The processor 21 may control operations of the whole memory controller20. For example, the processor 21 issues a read command in response to aread command received from the host apparatus 2, and transmits theissued command to the NAND interface circuit 26. Furthermore, theprocessor 21 may execute a patrol operation on the basis of count of thetimer 24. For example, the patrol operation is executed irrespective ofthe command from the host apparatus 2, and this operation contributes todecrease of read errors in the memory system 1. Description will be madeas to the patrol operation later in detail. It is to be noted that theprocessor 21 may execute various types of processing to manage a memoryspace of the NAND-type flash memory 10, for example, wear leveling andthe like. The processor 21 may instruct the NAND-type flash memory 10 toexecute an erase operation on the basis of an instruction for garbagecollection from the host apparatus 2. Alternatively, for example, whenthe number of free blocks is smaller than a predetermined number, theprocessor 21 may execute the garbage collection irrespective of theinstruction from the host apparatus 2, and may instruct the NAND-typeflash memory 10 to execute the erase operation.

The internal memory 22 is a memory area for use as a work area of theprocessor 21. For example, in the internal memory 22, there storedparameters to manage the NAND-type flash memory 10, various managementtables, and the like. For example, the internal memory 22 holds a queue(command queue) of the commands received from the host apparatus 2.Furthermore, the internal memory 22 holds an address conversion table toconvert, to a physical address of the block BLK, a logical addressassociated with the data stored in the block BLK. This addressconversion table is stored, for example, in the semiconductor memory 10,and is loaded into the internal memory 22 when the memory system 1starts up. As the internal memory 22, for example, a volatile memorysuch as the SRAM (static random access memory) is used.

The host interface circuit 23 is connected to the host apparatus 2, tomanage communication between the memory system 1 and the host apparatus2. For example, the host interface circuit 23 controls the transfer ofthe data, command and address between the memory system 1 and the hostapparatus 2. The host interface circuit 23 supports a communicationinterface standard such as SATA (serial advanced technology attachment),SAS (serial attached SCSI), or PCIe (PCI express) (registeredtrademark). That is, an example of the host apparatus 2 connected to thememory system 1 is a computer or the like including the interface ofSATA, SAS, PCIe or the like.

The timer 24 may measure a time associated with any operation of thememory system 1. For example, the timer 24 measures a period in whichthe patrol operation of one cycle is executed. “The patrol operation ofone cycle” corresponds to execution of a dummy read (described later)once for each block BLK targeted for the patrol operation. In thefollowing description, the period in which this patrol operation of onecycle is executed will be referred to as a patrol period.

The thermometer 25 may measure a system temperature of the memory system1. Specifically, the thermometer 25 measures the temperature of a regionwhere the thermometer 25 is disposed, thereby indirectly measuring atemperature of the whole memory controller 20 or a temperature of theNAND-type flash memory 10. The measured temperature is referred to bythe processor 21, for example, during the patrol operation.

The NAND interface circuit 26 is connected to the NAND-type flash memorychips 10A and 10B, and manages communication between the memorycontroller 20 and the NAND-type flash memory 10. The NAND interfacecircuit 26 is constituted on the basis of a NAND interface standard.

The DRAM interface circuit 27 is connected to the DRAM 11, and managescommunication between the memory controller 20 and the DRAM 3. The DRAMinterface circuit 27 is constituted on the basis of a DRAM interfacestandard. It is to be noted that the constitution of the DRAM interfacecircuit 27 is not limited to this example, and may be changed on thebasis of a type of volatile memory of the memory system 1.

It is to be noted that the above-mentioned constitution of the memorycontroller 20 is merely an example, and is not limited to this example.For example, the timer 24 and the thermometer 25 do not have to becontained in the memory controller 20, and may externally be connectedto the memory controller 20. Furthermore, the thermometer 25 may becontained in the NAND-type flash memory 10.

In the above-mentioned memory controller 20, the processor 21 loads aprogram associated with the patrol operation into the internal memory22, and executes the program. FIG. 6 shows a detailed exampleconstitution of the processor 21 during the patrol operation. As shownin FIG. 6, the processor 21 functions as a patrol controller portion 50and a command issue portion 51 during the patrol operation.

The patrol controller portion 50 sets the patrol period during which thepatrol target block contained in the memory cell array 11 is visited atleast once. Patrol periods are set repeatedly one after another, and,for example, a patrol period and its subsequent patrol period may besuccessive or continuous. Then, the patrol controller portion 50instructs the command issue portion 51 to execute a dummy read to ablock BLK targeted for the patrol operation every patrol period. In thefollowing description, the block BLK of the target for the patroloperation will be referred to as a patrol target block. It is to benoted that the patrol target blocks may be all the blocks BLKs in thememory cell array 11, or some blocks out of all the blocks BLKs.Furthermore, in the present description, the dummy read operation is,for example, an operation in which the read voltage or the read passvoltage is applied to a word line WL described with reference to FIG. 4,or the like. Specifically, in the dummy read operation of the presentdescription, data output operation (i.e., data transfer) from theNAND-type flash memory 10 via the NAND interface circuit 26 may not beperformed. In a normal read operation, in contrast, the data outputoperation is required for ECC (error correcting code) decoding.

The command issue portion 51 issues a command and an address concerningthe dummy read on the basis of the command from the patrol controllerportion 50. The issued command and address are transferred to theNAND-type flash memory 10 via the NAND interface circuit 26.

It is to be noted that there has been described above the example wherethe command issue portion 51 issues the command and address concerningthe dummy read, but the present invention is not limited to thisexample. For example, commands and addresses associated with variousoperations may be issued by the NAND interface circuit 26 on the basisof the control of the processor 21.

[1-2] Operation

In the memory system 1 according to the first embodiment, the memorycontroller 20 spontaneously executes (i.e., not driven by the host) thepatrol operation. Hereinafter, description will be made as to an examplewhere the memory controller 20 executes the patrol operation to oneNAND-type flash memory 10.

In the patrol operation, the dummy read is executed to the patrol targetblock every patrol period. Specifically, while the processor 21 executesthe operation based on the command from the host apparatus 2 in eachpatrol period, the patrol controller portion 50 instructs the NAND-typeflash memory 10 to execute the dummy read via the command issue portion51. Then, in the first embodiment, the patrol controller portion 50changes a patrol processing rate on the basis of remaining time of thepatrol period. The patrol processing rate indicates the number of theblocks BLKs being patrolled per unit time.

Hereinafter, description will be made as to the patrol period in detailwith reference to FIG. 7. FIG. 7 is a flow chart showing an example ofthe patrol operation in the memory system according to the firstembodiment, and shows an operation example of the memory system 1 in thepatrol period.

As shown in FIG. 7, when the patrol period starts, the processor 21initially determines whether or not the memory controller 20 hasreceived a command from the host apparatus 2 (step S10).

When the memory controller 20 has received a command from the hostapparatus 2 (YES in the step S10), the processor 21 executes anoperation based on the command from the host apparatus 2 (step S11).Examples of the operation based on the command from the host apparatus 2include the read operation and the write operation.

When the operation based on the command from the host apparatus 2 ends,the patrol controller portion 50 updates the patrol processing rate(step S12). Specifically, the patrol controller portion 50 updates thepatrol processing rate so that the dummy read to the patrol target blockis completed in the patrol period on the basis of the remaining time ofthe patrol period.

Then, the patrol controller portion 50 executes the dummy read on thebasis of the updated patrol processing rate (step S13). Specifically,the patrol controller portion 50 transmits a command for the dummy readto the command issue portion 51, and on the basis of the command, thecommand issue portion 51 issues the command and the address. Then, thecommand issue portion 51 transmits the issued command and address to theNAND-type flash memory 10 via the NAND interface circuit 26, and theNAND-type flash memory 10 executes the dummy read on the basis of itsreceived command and address.

When the memory controller 20 has not received a command from the hostapparatus 2 (NO in the step S10), the patrol controller portion 50executes the dummy read in the step S13 on the basis of a predeterminedpatrol processing rate. When this patrol processing rate is updated inthe step S12, the updated patrol processing rate is applied, and whenthe operation in the step S12 is not executed, a patrol processing ratecalculated on the basis of the length of the patrol period is applied.

When the dummy read in the step S13 ends, the patrol controller portion50 determines whether or not the dummy read to all the patrol targetblocks is completed (step S14).

When the dummy read to all the patrol target blocks is not completed (NOin the step S14), the processor 21 goes back to the operation of thestep S10, and repeatedly executes the operations of the steps S10through S14.

When the dummy read to all the patrol target blocks is completed (YES inthe step S14), the processor 21 ends the patrol operation in the patrolperiod. When the patrol period ends and the next patrol period begins,the patrol controller portion 50 executes the above operations of thesteps S10 through S14 again.

FIG. 8 shows an example of the transition of the patrol processing ratein the above-mentioned patrol period. FIG. 8 shows the example in a casewhere host read is executed in the middle of the patrol period in thepatrol operation described with reference to FIG. 7. In FIG. 8, theordinate indicates the patrol processing rate, and the abscissaindicates time.

As shown in FIG. 8, the patrol period starts at time t0, and the patrolcontroller portion 50 sets the patrol processing rate to, e.g., 10(BLKs/sec). This patrol processing rate is set to a value at which thedummy read to all the patrol target blocks can be completed, when theoperation based on the command of the host apparatus 2 is not executedin the patrol period. When the host read is executed at time t1, thedummy read based on the patrol operation does not progress due to theoperation based on the command of the host apparatus 2, and hence, thepatrol processing rate is 0 (BLKs/sec). When the host read ends at timet2, the patrol controller portion 50 sets the patrol processing rate to,e.g., 30 (BLKs/sec). Then, the dummy read to all the patrol targetblocks is completed by time t3, and the patrol period ends. In this way,the patrol processing rate at the time t2 through t3 after the host readis executed is set to be higher than the patrol processing rate at thetime t0 through t1 before the host read is executed.

To change the patrol processing rate, a method changing the priority toexecute the dummy read over the host read, or a method changing thenumber of blocks BLKs being selected (i.e., activated) in one executionof the dummy read may be employed. Hereinafter, description will be madeas to a first dummy read in which one block BLK is selected (i.e.,activated) and a second dummy read in which a plurality of blocks BLKsare selected (i.e., activated).

Initially, description will be made in detail as to the first dummy readwith reference to FIG. 9. FIG. 9 shows examples of a command sequenceand a waveform of the first dummy read, and shows commands in theinput/output signal I/O, a waveform of the ready/busy signal RBn and awaveform of the word line WL.

As shown in FIG. 9, the memory controller 20 initially issues a command“xxh” to transmit the command to the NAND-type flash memory 10, and theNAND-type flash memory 10 holds the received command “xxh” in thecommand register 15C. The command “xxh” is a command to execute theoperation of the SLC mode. Next, the memory controller 20 issues acommand “00h” to transmit the command to the NAND-type flash memory 10,and the NAND-type flash memory 10 holds the received command “00h” inthe command register 15C. The command “00h” corresponds to an addressinput reception command for reading, and also to instruct the NAND-typeflash memory 10 to execute the reading of the data. Next, the memorycontroller 20 transmits the address information ADD to the NAND-typeflash memory 10, and the NAND-type flash memory 10 holds the receivedaddress information ADD in the address register 15B. This addressinformation ADD designates an address of the target for the first dummyread and, for example, the word line WL (e.g., the word line WL7 shownin FIG. 5) disposed in an uppermost layer of the block BLK is selected.The word line WL to be selected in the first dummy read is not limitedto this example, and another word line WL may be selected. Next, thememory controller 20 transmits a command “30h” to the NAND-type flashmemory 10, and the NAND-type flash memory 10 holds the received command“30h” in the command register 15C. The command “30h” is a command forthe sequencer 17 to execute the first dummy read on the basis of thepreceding command CMD and address information ADD. When the command“30h” is held in the command register 15C, the sequencer 17 changes theready/busy signal RBn from an “H”-level to an “L”-level and holds, whileexecuting the first dummy read.

In the first dummy read, the row decoder module 13 applies the readvoltage AR to the selected word line WL, and applies the read passvoltage VREAD to the non-selected word line WL. Then, the voltage of theselected word line WL rises, for example, from a ground voltage VSS upto the read voltage AR, and the voltage of the non-selected word line WLrises, for example, from the ground voltage VSS to the read pass voltageVREAD. Then, the row decoder module 13 applies the voltages for apredetermined time, and lowers the voltages of the selected andnon-selected word lines WLs down to the ground voltage VSS. Then, thesequencer 17 changes the ready/busy signal RBn from the “L”-level to the“H”-level, to notify the memory controller 20 of the end of the firstdummy read. It is to be noted that in the following description, aperiod in which the ready/busy signal RBn has the “L”-level during thefirst dummy read will be referred to as a period T1.

A command set to execute the above-mentioned first dummy read is similarto, for example, a command set to execute the read operation of the SLCmode. That is, the operation of the NAND-type flash memory 10 in thefirst dummy read is similar to the read operation of the SLC mode. It isto be noted that the data read by the NAND-type flash memory 10 in thefirst dummy read may be or does not have to be transferred to the memorycontroller 20.

Next, description will be made as to the second dummy read in detailwith reference to FIG. 10. FIG. 10 shows examples of a command sequenceand a waveform in the second dummy read, and shows a command in theinput/output signal I/O, a waveform of the ready/busy signal RBn and awaveform of the word line WL.

As shown in FIG. 10, the memory controller 20 initially issues a command“yyh” to transmit the command to the NAND-type flash memory 10, and theNAND-type flash memory 10 holds the received command “yyh” in thecommand register 15C. The command “yyh” is a command to execute thedummy read for selected blocks BLKs. Next, the memory controller 20transmits the address information ADD to the NAND-type flash memory 10,and the NAND-type flash memory 10 holds the received address informationADD in the address register 15B. This address information ADD designatesthe blocks BLKs targeted for the second dummy read, and the informationmay include address information to designate multiple blocks BLKs. Whenthe address information ADD is held in the address register 15B, thesequencer 17 changes the ready/busy signal RBn from the “H”-level to the“L”-level, to execute the second dummy read.

In the second dummy read, the row decoder module 13 applies, forexample, the read pass voltage VREAD to all the word lines WLscorresponding to the selected blocks BLKs. Then, voltages of theselected (i.e., all) word lines WLs in the selected blocks BLKs risefrom the ground voltage VSS up to the read pass voltage VREAD. At thistime, a time necessary for the voltage of the word line WL to rise fromthe ground voltage VSS up to the read pass voltage VREAD is longer thanthat in the first dummy read. Then, the row decoder module 13 appliesthe read pass voltage VREAD to the word line WL for a predeterminedtime, and then lowers the voltage of the word line WL down to the groundvoltage VSS. Then, the sequencer 17 changes the ready/busy signal RBnfrom the “L”-level to the “H”-level, to notify the memory controller 20of the end of the second dummy read. A period T2 in which the ready/busysignal RBn has the “L”-level during the second dummy read is longer thanthe period T1. That is, the time necessary to execute the second dummyread is longer than the time necessary to execute the first dummy read.Furthermore, even in the same second dummy read, the time necessary toexecute the second dummy read tends to be long, as the number of theselected blocks BLKs increases.

As described above, the first dummy read is different from the seconddummy read in the number of the blocks BLKs being patrolled on the basisof one command of the memory controller 20. In the second dummy read,the number of the blocks BLKs being patrolled at a time is large, andhence, the patrol processing rate in the case of employing the seconddummy read is generally higher than the patrol processing rate in thecase of employing the first dummy read. Therefore, for example, thememory controller 20 employs the first dummy read when the patrolprocessing rate is to be lowered, and the memory controller employs thesecond dummy read when the patrol processing rate is to be raised.

For example, when the command of the host apparatus 2 collides with thecommand for the dummy read and when an access frequency from the hostapparatus 2 to the memory system 1 is low, decreasing throughput of thedummy read generally improves latency for commands from the hostapparatus 2. On the other hand, when the access frequency from the hostapparatus 2 to the memory system 1 is high, increase of the throughputof the dummy read generally improves the latency. Therefore, the patrolcontroller portion 50 properly selects and uses the first dummy read andthe second dummy read, for example, on the basis of the access frequencyfrom the host apparatus 2.

Hereinafter, description will be made as to the present example withreference to FIG. 11. FIG. 11 shows an example of a selection criterionof a dummy read process in the patrol period, and shows a state of thecommand queue held in the internal memory 22. In the present example,the patrol controller portion 50 provides a threshold with respect to aqueue length, thereby properly using the first dummy read and the seconddummy read. The queue length indicates a number of commands queued inthe internal memory 22. Specifically, a current number of commands heldin the queue is denoted by a current queue length, or simply a queuelength. A (current) queue length may be denoted by a (current) queuedepth. Note that a queue length may be measured with respect to a sum ofdata amounts corresponding to the commands, instead of the number (i.e.,the count) of commands. Hereinafter, the threshold provided in the queuelength will be referred to as a queue threshold. The queue threshold maybe set to any value.

As shown in FIG. 11, in Case 1, the queue length corresponding to a readcommand by the host apparatus 2 is not more than the queue threshold.This state indicates, for example, that the access frequency from thehost apparatus 2 to the memory system 1 is low. In this case, the patrolcontroller portion 50 selects, for example, the first dummy read as asubsequent dummy read process, and appends, to the command queue, acommand to execute the first dummy read.

In Case 2, the queue length corresponding to the read command by thehost apparatus 2 is in excess of the queue threshold. This stateindicates, for example, that the access frequency from the hostapparatus 2 to the memory system 1 is high. In this case, the patrolcontroller portion 50 selects, for example, the second dummy read forthe subsequent dummy read process, and adds, to the command queue, acommand to execute the second dummy read.

As described above, the patrol controller portion 50 executes the firstdummy read in which a processing time is comparatively short, when theaccess frequency from the host apparatus 2 is low, and the patrolcontroller portion executes the second dummy read in which a processingtime is long, when the access frequency is high. Consequently, thememory system 1 can inhibit deterioration of the latency that occurswhen the command of the host apparatus 2 collides with the command toexecute the dummy read. It is to be noted that the patrol controllerportion 50 may properly select and use the first dummy read and thesecond dummy read on the basis of a maximal number of commands that canbe held in the queue at a time by the memory controller 20 (i.e., amaximal queue length, or a maximal queue depth).

A method for selecting a dummy read method from among the first dummyread and the second dummy read is not limited to this example. Forexample, the patrol controller portion 50 may select on the basis of arequired patrol processing rate.

It is to be noted that there has been described above the example wherethe dummy read to all the patrol target blocks is completed in thepatrol period, but the present invention is not limited to this example.For example, when the commands from the host apparatus 2 are frequentand successive, the dummy read to all the patrol target blocks is not becompleted in the patrol period in some cases. In this case, the patrolcontroller portion 50 may interrupt the command from the host apparatus2 to execute the dummy read, thereby performing the operation tocomplete the dummy read to all the patrol target blocks in the patrolperiod.

[1-3] Effect of First Embodiment

According to the memory system 1 of the above-mentioned firstembodiment, it is possible to inhibit occurring of retry read during theread operation. Hereinafter, description will be made as to a detailedeffect of the memory system 1 according to the first embodiment.

For example, as shown in FIG. 5, in the NAND-type flash memory 10 inwhich the memory cells are stacked in three dimensions, channels of thememory cell transistors MTs constituting the NAND string NS have astructure where the conductive semiconductor material 40 is shared. Inthe NAND-type flash memory 10 of such a structure, a phenomenonoccasionally occurs, a phenomenon as shown in FIG. 12, for example,occasionally occurs. FIG. 12 shows examples of the word line WL duringthe read operation and a waveform in the channel of the NAND string NS.

As shown in FIG. 12, when the read operation is executed, the rowdecoder module 13 applies the read pass voltage VREAD to thenon-selected word line WL of the selected block BLK. Then, when the readdata is determined, the row decoder module 13 lowers the voltage of thenon-selected word line WL down to the ground voltage VSS. At this time,when the voltage of the word line WL is not more than the thresholdvoltage of the memory cell transistor MT, the memory cell transistor MTis turned off. Then, when the voltage of the word line WL furtherlowers, a channel potential of the NAND string NS lowers from the groundvoltage to a negative voltage due to coupling with the word line WL. Theblock BLK is not selected after the read operation, and as a result, theword line WL comes into a floating state. In this state, when thenegative channel potential returns to the ground voltage on the basis ofelapse of time, the voltage of the word line WL rises up to, e.g., about4 V due to the coupling with the channel of the NAND string NS. FIG. 12shows this phenomenon as “creep up”.

In the block BLK in which the voltage of the word line WL creeps up torise, a potential difference is made between the control gate of thememory cell transistor MT and the channel in the block BLK, and thethreshold voltage occasionally changes on the basis of the elapse oftime (e.g., from 10 through 100 ms) after the read operation.

Then, the voltage of the word line WL which has creeped up returns tothe ground voltage on the basis of the elapse of time as shown in FIG.12. With further elapse of the time (e.g., from about several minutes toseveral hours) after fluctuations of the voltage of the word line WL dueto the creep up phenomenon are settled, the threshold voltage of thememory cell transistor MT which has risen returns to its original state.In this way, the memory cell transistor MT may take two states, i.e., afirst state where the threshold voltage has an initial state and asecond state where the threshold voltage changes due to an influence ofthe creep up phenomenon. On the other hand, the read voltage isoptimized to be set to the second state, and hence, in the NAND-typeflash memory 10 in which the creep up phenomenon might occur, it ispreferable to maintain the memory cell transistor MT in the secondstate.

Therefore, in the memory system 1 according to the first embodiment, thememory controller 20 periodically executes the dummy read to theNAND-type flash memory 10. Specifically, the patrol controller portion50 sets the patrol period to be shorter than a time necessary for thememory cell transistor MT to transition from the second state to thefirst state, and the patrol controller portion 50 instructs theNAND-type flash memory 10 to execute the dummy read to the patrol targetblock every patrol period.

More specifically, for example, the patrol controller portion 50executes the dummy read to the block BLK including the memory celltransistor MT of the first state. Then, the creep up phenomenon occursin the block BLK subjected to the dummy read, and the memory celltransistor MT transitions from the first state to the second state.Then, the patrol controller portion 50 executes the dummy read to theblock BLK including the memory cell transistor MT of the second stateagain, before the memory cell transistor MT transitions from the secondstate to the first state on the basis of the elapse of time. Then, thecreep up phenomenon occurs again in the block including the memory celltransistor MT of the second state, and the voltage of the word line WLrises. When a creep up voltage is applied to a gate electrode of thememory cell transistor MT of the second state, the memory celltransistor MT comes in a state similar to the state where the transistortransitions from the first state to the second state. Afterward, thepatrol controller portion 50 executes the dummy read to each block BLKbefore the memory cell transistor MT transitions from the second stateto the first state, whereby the memory cell transistor MT of the secondstate is maintained in the second state.

Consequently, the memory system 1 of the first embodiment can executethe read operation to the memory cell transistor MT maintained in thesecond state. Therefore, in the memory system 1 according to the firstembodiment, it is possible to inhibit increase of error bits which iscaused due to the influence of the fluctuation in threshold voltage ofthe memory cell transistor MT, and occurrence of the retry read which iscaused due to the increase of the error bits. That is, in the memorysystem 1 according to the first embodiment, it is possible to inhibitdrop of an operation speed which is caused by read errors.

[2] Second Embodiment

A memory system 1 according to a second embodiment can operate in, forexample, a normal operation mode and a low power consumption mode. Thememory system 1 in the normal operation mode can execute a command froma host apparatus 2. In the memory system 1 of the low power consumptionmode, some of the modules of the memory system 1 that are active in thenormal operation mode are inactive. Power consumption of the memorysystem 1 in the low power consumption mode is lower than that in thenormal operation mode. Furthermore, the memory system 1 of the secondembodiment spontaneously executes a patrol operation in the low powerconsumption mode. Hereinafter, description will be made as todifferences of the memory system 1 according to the second embodimentfrom the memory system according to the first embodiment.

[2-1] Constitution

When the memory system 1 according to the second embodiment receives,for example, a predetermined command from a host apparatus 2 or whenthere are no commands from the host apparatus 2 over a predeterminedperiod, the system spontaneously transitions to the low powerconsumption mode. In the memory system 1 in the low power consumptionmode, only limited modules are supplied with power (i.e., active) tosuppress power consumption, whereas the power supply to a part of aprocessor 21 and a timer 24 in a memory controller 20 is maintained.

FIG. 13 shows a detailed example constitution of the processor 21 in thelow power consumption mode. As shown in FIG. 13, the processor 21according to the second embodiment functions as a first patrolcontroller portion 50A, a second patrol controller portion 50B, and acommand issue portion 51.

The first patrol controller portion 50A and the second patrol controllerportion 50B are similar to, for example, the patrol controller portion50 described in the first embodiment with reference to FIG. 6. In thelow power consumption mode, the power supply to the first patrolcontroller portion 50A is stopped, and the first patrol controllerportion 50A comes in a low power consumption (i.e., inactive) statewhere power consumption is lower than that in a normal operation. In thelow power consumption mode, for example, the second patrol controllerportion 50B is maintained active and monitors progress of dummy read ineach patrol period on the basis of count of the timer 24. Then, forexample, when the progress of the dummy read is behind predeterminedprogress in the patrol period, the second patrol controller portion 50Bresumes power supply to the command issue portion 51, a NAND interfacecircuit 26 and a NAND-type flash memory 10 to activate them therebyinstructing the command issue portion 51 to execute the dummy read to apatrol target block. Furthermore, the second patrol controller portion50B manages a number Ncompleted of the patrolled blocks BLKs in thepatrol period. The number Ncompleted of the patrolled blocks BLKs isheld in an internal memory 22, and is updated by the second patrolcontroller portion 50B as the dummy read proceeds.

The command issue portion 51 is similar to the command issue portion 51described in the first embodiment with reference to FIG. 6. In the lowpower consumption mode, the command issue portion 51 resumes from theinactive state to the active state on the basis of a command from thesecond patrol controller portion 50B, and on the basis of the command ofthe second patrol controller portion 50B, the command issue portionissues a command and an address concerning the dummy read. The issuedcommand and address are transferred to the NAND-type flash memory 10 viathe NAND interface circuit 26, and the NAND-type flash memory 10executes the dummy read on the basis of the command and the address. Therest of constitution of the memory system 1 according to the secondembodiment is similar to the constitution of the memory system 1according to the first embodiment, and hence, description is omitted.

[2-2] Operation

FIG. 14 is a flow chart showing an example of the patrol operation inthe memory system 1 according to the second embodiment, and shows anoperation example of the memory system 1 in the low power consumptionmode.

As shown in FIG. 14, when the low power consumption mode starts, thesecond patrol controller portion 50B initially obtains the number of thepatrolled blocks BLKs (step S20), and determines whether the numberNcompleted of the patrolled blocks BLKs is not more than a predeterminedthreshold Nthreshold (step S21). The predetermined threshold Nthresholdmay be set on the basis of remaining time of the patrol period.

When Ncompleted is in excess of Nthreshold (Ncompleted>Nthreshold) (NOin the step S21), the second patrol controller portion 50B goes back tothe step S20, and repeats comparison between the number Ncompleted ofthe patrolled blocks BLKs and the threshold Nthreshold which varies onthe basis of elapse of time.

When Ncompleted is less than or equal to Nthreshold(Ncompleted≤Nthreshold) (YES in the step S21), the second patrolcontroller portion 50B activates the command issue portion 51, the NANDinterface circuit 26 and the NAND-type flash memory 10 from the inactive(e.g., low power) state to the active (e.g., normal) state to executethe dummy read to which a predetermined patrol processing rate isapplied. The mode in which the memory system 1 is able to perform thepatrol operation is referred to as a partially-active low power mode.For example, this dummy read is similar to the dummy read in the stepS13 described in the first embodiment with reference to FIG. 7.

Then, the second patrol controller portion 50B again obtains the numberNcompleted of the patrolled blocks BLKs (step S23), and determineswhether the number Ncompleted of the patrolled blocks BLKs is not lessthan a target value Ntarget (step S24). The target value Ntarget is avalue higher than the threshold Nthreshold, and is set so that the dummyread to all the patrol target blocks is completed in the patrol period.

When Ncompleted is less than Ntarget (Ncompleted<Ntarget) (NO in thestep S24), the second patrol controller portion 50B goes back to thestep S13, and repeats the dummy read to which the predetermined patrolprocessing rate is applied and the monitoring of the number Ncompletedof the patrolled blocks BLKs.

When Ncompleted is not less than Ntarget (Ncompleted≥Ntarget) (YES inthe step S24), the second patrol controller portion 50B causes thecommand issue portion 51, the NAND interface circuit 26 and theNAND-type flash memory 10 to transition to the inactive state, and thememory system 1 returns from the partially-active low power mode to theoriginal low power consumption mode (referred to as an inactive lowpower consumption mode). That is, the second patrol controller portion50B goes back to the step S20, and repeatedly executes theabove-mentioned operation.

FIG. 15 shows an example of the patrol operation in the above-mentionedlow power consumption mode. FIG. 15 shows an example of transition ofthe number of the patrolled blocks BLKs in the patrol period of the lowpower consumption mode, the ordinate indicates the number Ncompleted ofthe patrolled blocks BLKs, and the abscissa indicates time. Furthermore,FIG. 15 shows transition of the predetermined threshold Nthreshold withrespect to time and transition of the target threshold Ntarget with timeby broken lines, and n blocks BLKs are designated as the patrol targetblocks.

As shown in FIG. 15, Ncompleted is “0” (there are no patrolled blocksBLKs) at time to. Then, Ncompleted is not more than Nthreshold at timet1. In this case, the second patrol controller portion 50B activatesassociated modules from the inactive state to the active state, andexecutes the dummy read at a predetermined patrol processing rate. WhenNcompleted is not less than Ntarget at time t2, the second patrolcontroller portion 50B deactivates the associated modules to transitionto the inactive state, and the memory system 1 returns from thepartially-active low power consumption mode to the inactive low powerconsumption mode (i.e., the original low power consumption mode).Afterward, such an operation is repeatedly executed. Briefly, the secondpatrol controller portion changes conditions of the associated moduleson the basis of a progress situation of the dummy read, to execute thedummy read at time t3, stop the dummy read at time t4, and execute thedummy read at time t5. Then, at time t6, when Ncompleted reaches thenumber of the patrol target blocks, the second patrol controller portion50B ends the patrol operation in the patrol period.

Additionally, there has been described above the example where thesecond patrol controller portion 50B instructs the execution of thedummy read in the low power consumption mode on the basis of results ofthe comparison between the number Ncompleted of the patrolled blocksBLKs and the predetermined threshold Nthreshold, but the presentinvention is not limited to this example. For example, in the low powerconsumption mode, the second patrol controller portion 50B mayperiodically instruct the execution of the dummy read on the basis ofthe count of the timer 24 as shown in FIG. 16. FIG. 16 is a flow chartshowing a modified example of the patrol operation in the memory system1 according to the second embodiment, and shows an operation example ofthe memory system 1 in the low power consumption mode.

When the low power consumption mode starts as shown in FIG. 16, thesecond patrol controller portion 50B initially obtains the count of thetimer 24 (step S30), and determines whether or not a predetermined timeelapses (step S31).

When the count of the timer 24 does not indicate the predetermined timehas elapsed (NO in the step S31), the second patrol controller portion50B goes back to the step S30, and continues the monitoring of the countof the timer 24.

When the count of the timer 24 indicates the predetermined time haselapsed (YES in the step S31), the second patrol controller portion 50Bactivates the command issue portion 51, the NAND interface circuit 26and the NAND-type flash memory 10 from the inactive state to the activestate to execute the dummy read to which the predetermined patrolprocessing rate is applied. For example, this dummy read is similar tothe dummy read in the step S13 described in the first embodiment withreference to FIG. 7.

When the dummy read in the step S13 ends, the second patrol controllerportion 50B deactivates the command issue portion 51, the NAND interfacecircuit 26 and the NAND-type flash memory 10 to transition from theactive state to the inactive state, and the memory system 1 returns fromthe partially-active low power consumption mode to the inactive lowpower consumption mode. That is, the second patrol controller portion50B goes back to the step S30, and repeatedly executes theabove-mentioned operation.

Additionally, for example, the predetermined time in the step S31 is setso that the dummy read to the patrol target block is completed in thepatrol period. Also by using this method, in the memory system 1, it ispossible to perform the dummy read in the patrol period in the low powerconsumption mode as shown in FIG. 15.

[2-3] Effect of Second Embodiment

According to the memory system 1 of the above-mentioned secondembodiment, it is possible to inhibit drop of an operation speed whenthe system returns from the low power consumption mode. Hereinafter,description will be made as to a detailed effect of the memory system 1according to the second embodiment.

The memory system 1 occasionally transitions to the low powerconsumption mode, for example, when there are no commands from the hostapparatus 2 for a long time, or when a power mode switch command fromthe host apparatus 2 is received. In the low power consumption mode, themodules to which power is to be supplied are limited to suppress powerconsumption, and hence, for example, the patrol operation described inthe first embodiment occasionally stops.

To solve such a problem, in the memory system 1 according to the secondembodiment, the dummy read is periodically executed also in the lowpower consumption mode. Specifically, for example, the second patrolcontroller portion 50B and the timer 24 in the memory controller 20operate even in the low power consumption mode. In the low powerconsumption mode, the second patrol controller portion 50B detects, forexample, that the number of the patrolled blocks BLKs is smaller than apredetermined value in the patrol period or that the predetermined timehas elapsed on the basis of the count of the timer 24. Then, the patrolcontroller portion 50B temporarily wakes up the predetermined modules ofthe memory system 1 from the inactive state to the active state, andinstructs the NAND-type flash memory 10 to execute the dummy read.

Consequently, in the memory system 1 according to the second embodiment,it is possible to inhibit the transition of the memory cell transistorMT of the patrol target block to the first state in the low powerconsumption mode. Therefore, in the memory system 1 according to thesecond embodiment, it is possible to inhibit occurrence of retry read inthe read operation when the system wakes up from the low powerconsumption mode, and hence, it is possible to inhibit the drop of theoperation speed.

[3] Third Embodiment

In a memory system 1 according to a third embodiment, a length of apatrol period is changed on the basis of a temperature state of thememory system 1. Hereinafter, description will be made as to differencesof the memory system 1 according to the third embodiment from the firstand second embodiments.

[3-1] Constitution

FIG. 17 shows a detailed example constitution of a processor 21 in thecase of changing the patrol period on the basis of the temperaturestate. As shown in FIG. 17, in the third embodiment, the processor 21inputs information of a thermometer 25 into a patrol controller portion50 described in the first embodiment with reference to FIG. 6. Then, thepatrol controller portion 50 in the third embodiment changes the patrolperiod on the basis of temperature information from the thermometer 25.The rest of constitution of the memory system 1 according to the thirdembodiment is similar to the constitution of the memory system 1according to the first embodiment, and hence, description is omitted.

[3-2] Operation

FIG. 18 is a flow chart showing an example of a patrol operation in thememory system 1 according to the third embodiment, and shows anoperation example of the memory system 1 based on the temperature state.

As shown in FIG. 18, when the patrol period starts, the patrolcontroller portion 50 initially acquires the temperature informationfrom the thermometer 25 to obtain a system temperature of the memorysystem 1 (step S40). Next, the patrol controller portion 50 calculates asystem temperature on the basis of, for example, the acquiredtemperature information, and sets the length of the patrol period on thebasis of the calculated system temperature (step S41). Specifically, forexample, when the system temperature is equal to or higher than apredetermined temperature, the patrol period is set to be longer than aninitial value, and when the system temperature is higher than thepredetermined temperature, the patrol period is set to be shorter thanthe initial value.

It is to be noted that a method in which the patrol controller portion50 sets the length of the patrol period is not limited to this example.In the method of setting the patrol period, the length of patrol periodmay be determined on the basis of the acquired temperature information,there may be referred to a table in which a range of the systemtemperature is associated with the length of the patrol period, or thelength of the patrol period may be calculated from a value of the systemtemperature by using a predetermined formula.

Then, for example, the patrol controller portion 50 executes the patroloperation of the steps S10 through S14 described in the first embodimentwith reference to FIG. 7, in the set patrol period. When the patrolperiod ends and the next patrol period begins, the patrol controllerportion 50 goes back to the step S40, and repeatedly executes theabove-mentioned operation. It is to be noted that the patrol controllerportion 50 may further measure a temperature in the middle of the patrolperiod and update the patrol period.

FIG. 19 shows an example of the patrol operation based on theabove-mentioned temperature state. FIG. 19 shows an example oftransition of a patrol processing rate in the patrol operation based onthe temperature state, the ordinate indicates the patrol processingrate, and the abscissa indicates time. Furthermore, FIG. 19 shows twodifferent patrol periods (a first patrol period and a second patrolperiod), and a patrol processing rate in other patrol periods isomitted.

As shown in FIG. 19, when the system temperature of the memory system 1is 30° C. at time to, the patrol controller portion 50 sets a firstpatrol period T3 on the basis of this value of the system temperature.It is to be noted that in the present example, a period from the time t0to t1 corresponds to the patrol period T3. Then, the patrol controllerportion 50 sets the patrol processing rate to, for example, 10(BLKs/sec) on the basis of the length of the first patrol period T3, andexecutes the patrol operation.

When the temperature of the memory system 1 is 70° C. at time t2, thepatrol controller portion 50 sets a second patrol period T4 on the basisof this value of the system temperature. It is to be noted that in thepresent example, a period from the time t2 to t3 corresponds to thepatrol period T4, and the period T4 is set to be shorter than the periodT3. Then, the patrol controller portion 50 sets the patrol processingrate to, for example, 30 (BLKs/sec) on the basis of the length of thepatrol period T4, and executes the patrol operation. The period T4corresponds to the second patrol period and indicates a time from t2 tot3.

As described above, in the present example, the system temperature atthe time t2 is higher than the system temperature at the time to, andhence, for example, the second patrol period T4 is set to be shorterthan the first patrol period T3. Furthermore, the second patrol periodT4 is shorter than the first patrol period T3, and hence, for example,the patrol processing rate in the second patrol period is set to behigher than the patrol processing rate in the first patrol period.

[3-3] Effect of Third Embodiment

According to the memory system 1 of the above-mentioned thirdembodiment, it is possible to inhibit drop of an operation speed due toan influence of the change of the system temperature. Hereinafter,description will be made as to a detailed effect of the memory system 1according to the third embodiment.

A time necessary for a threshold voltage of a memory cell transistor MTto transition from a second state to a first state occasionally changeson the basis of the temperature state. For example, it is consideredthat when the system temperature of the memory system 1 is high, thetime necessary for the memory cell transistor MT to transition from thesecond state to the first state shortens, and when the systemtemperature is low, the time necessary for the memory cell transistor MTto transition from the second state to the first state lengthens.

To solve this problem, in the memory system 1 according to the thirdembodiment, the length of each patrol period is optimized on the basisof the temperature state of the memory system 1. Specifically, forexample, the patrol controller portion 50 of the processor 21 initiallyacquires the temperature information from the thermometer 25 containedin the memory controller 20. This temperature information indirectlyindicates the system temperature of the whole memory system 1 and thetemperature of the memory cell transistor MT in a NAND-type flash memory10. Then, the patrol controller portion 50 sets the length of eachpatrol period on the basis of the temperature information, and optimizesthe length of the patrol period on the basis of the temperature state.

For example, when the temperature of the memory system 1 is high and thetime necessary for the memory cell transistor MT to transition from thesecond state to the first state shortens, the patrol controller portion50 sets the short patrol period on the basis of this situation. On theother hand, when the temperature of the memory system 1 is low and thetime necessary for the memory cell transistor MT to transition from thesecond state to the first state lengthens, the patrol controller portion50 sets the long patrol period on the basis of this situation. Then, thepatrol controller portion 50 determines the patrol processing rate inthe set patrol period, and executes dummy read.

Consequently, in the memory system 1 according to the third embodiment,it is possible to avoid a situation where the dummy read is executed tothe memory cell transistor MT more than necessary or a situation where aread operation instructed by a host apparatus 2 is executed when thememory cell transistor MT has transitioned from the second state to thefirst state. Therefore, in the memory system 1 according to the thirdembodiment, it is possible to inhibit the drop of the operation speeddue to the influence of the change of the system temperature.

It is to be noted that in the memory system 1 according to the thirdembodiment, the thermometer may be contained in the NAND-type flashmemory 10. In this case, according to the memory system 1, it ispossible to set the length of each patrol period on the basis of thetemperature information measured with the thermometer contained in theNAND-type flash memory 10, and it is possible to optimize the length ofthe patrol period on the basis of the temperature state.

[4] Fourth Embodiment

In a memory system 1 according to a fourth embodiment, a processingorder for dummy read of patrol target blocks is determined on the basisof a priority. Hereinafter, description will be made as to differencesof the memory system 1 according to the fourth embodiment from the firstthrough third embodiments.

[4-1] Constitution

FIG. 20 shows a detailed example constitution of a DRAM 3 and aprocessor 21 in a case where the processing order for dummy read of thepatrol target blocks is determined on the basis of the priority. Asshown in FIG. 20, in the fourth embodiment, the DRAM 3 stores anattribute table 60, and the processor 21 further functions as a prioritydecision portion 52.

The attribute table 60 contains information associated with each blockBLK, and the processor 21 updates the attribute table 60 on the basis ofvarious operations of the memory system 1. Examples of the informationincluded in the attribute table 60 include a block state, a write mode,the number of write/erase cycles, the number of write times, last writetime, last access time, and the number of read errors. FIG. 21 shows anexample of the attribute table 60 including these pieces of information.

As shown in FIG. 21, there are blocks BLKs in which attributes of thedata being stored are different, and blocks BLK to which different writemethods are applied. Specifically, in the attribute table 60, theattribute of the information to be stored, e.g., a free block, an activeblock (storing user data) or an active block (storing debug information)attribute is recorded as the block state. Furthermore, in the attributetable 60, for example, MLC, SLC or the like is recorded as the writemode to be applied to the block BLK. In the attribute table 60, forexample, information of hours, minutes and seconds is recorded as thelast write time or the last access time, but the information is notlimited thereto, and the information of the last write time and lastaccess time recorded in the attribute table 60 may include informationof date. It is to be noted that the information included in theattribute table 60 is not limited to this example, and may include anyinformation concerned with the block BLK.

The priority decision portion 52 determines the priority of dummy readin the patrol period with reference to the attribute table 60 stored inthe DRAM 3. The priority is set to three levels, e.g., high, medium andlow levels. It is to be noted that the setting of the priority is notlimited to the three levels, and the priority may be set to any numberof levels. Hereinafter, description will be made as to an example of asetting criterion of the priority.

In a case where the priority is set on the basis of the attribute of theblock BLK, for example, the priority decision portion 52 lowers thepriority of a block BLK which is not to be a target of host read.

In a case where the priority is set on the basis of a reliability of theblock BLK, the priority decision portion 52 lowers the priority of theblock having a large reliability margin (e.g., a block to which the SLCmode is applied, a block protected with strong error correction, a blockin which the number of the write/erase cycles is small, or the like),and the portion raises the priority of an exhausted block (e.g., a blockin which the number of the write/erase cycles is large, a block in whichread disturb and/or data retention stress is large, or the like).

In a case where the priority of a region is set on the basis of anaccess profile, on the basis of the number of times of access to theregion out of the number of times of access to the entire space of thememory system 1 in terms of the number of commands and/or the dataamount as a criterion, the priority decision portion 52 lowers thepriority of a block having a low access frequency, and raises a priorityof a block of a high access frequency or a block accessed most recently.

In a case where the priority is set on the basis of a profile of timeviewpoint, by using a time interval between the access to the region andthe next access as a criterion, the priority decision portion 52 lowersa priority of a block including a logical block address at which anaccess interval is short (e.g., in the order of seconds) and a priorityof a block including a logical block address at which an access intervalis long (e.g., in the order of hours), and raises a priority of a blockincluding a logical block address at which an access interval is medium(e.g., in the order of minutes). For example, in the block having theshort access interval, a memory cell transistor MT can be maintained ina second state by the host read, and hence, its priority may be lowered.In the block having the long access interval, the access frequency islow, and, for example, importance of stored information is low, andhence, its priority may be lowered. In the block having the mediumaccess interval, it is difficult to maintain the transistor in thesecond state by the host read, there is the high possibility that theblock is accessed where the transistor is in a first state, and hence,its priority may be raised.

In a case where the priority is set on the basis of a profile in areliability viewpoint, for example, the priority decision portion 52raises the priority of a block having a high error rate as in a block inwhich the number of times of occurrence of retry read is large.

In the case of setting the priority on the basis of elapse of time, thepriority decision portion 52 raises the priority of a block in which acertain time or more elapses since when a write operation to the blockis executed or time when the dummy read is last executed to the block.

It is to be noted that the priority decision portion 52 may determinethe priority on the basis of one of the above-mentioned pieces of theinformation included in the attribute table 60 or a combination ofseveral pieces of the information. Furthermore, the priority decisionportion 52 may determine the priority on the basis of the information ofthe attribute table 60 and count of a timer 24. The rest of constitutionof the memory system 1 according to the fourth embodiment is similar tothe constitution of the memory system 1 according to the firstembodiment, and hence, description is omitted.

Additionally, there has been described above the example where theattribute table 60 is stored in the DRAM 3, but the present invention isnot limited to this example. For example, the attribute table 60 may bestored in an internal memory 22 of the memory controller 20.Alternatively, the attribute table 60 may be stored in the NAND-typeflash memory 10, and may be read out from the NAND-type flash memory 10into the DRAM 3 or the internal memory 22.

[4-2] Operation

FIG. 22 shows an example of a patrol operation based on the priority inthe fourth embodiment, and shows the priority of the patrol target blockfor the dummy read along a time axis. Furthermore, FIG. 22 shows a firstpatrol period, and a second patrol period which follows the first patrolperiod.

As shown in FIG. 22, in the first patrol period, a patrol controllerportion 50 executes the dummy read on the basis of the priority of thepatrol target block which is determined by the priority decision portion52. Specifically, in the first patrol period, the patrol controllerportion 50 executes the dummy read to the patrol target blocks in orderof priority from higher to lower.

In the following second patrol period, the patrol controller portion 50executes the dummy read to the patrol target blocks in a priority ordersimilar to that of the first patrol period. In the second patrol periodof the present example, an operation (e.g., the host read) based on acommand from a host apparatus 2 is executed after the dummy read to thepatrol target block having the high priority is executed. In this way,when a remaining time of the patrol period shortens due to the operationbased on the command from the host apparatus 2 in the patrol period, thepatrol period occasionally ends before the dummy read to the patroltarget block having the low priority is executed.

Additionally, there has been described above the example where the dummyread to the patrol target block of the low priority is not executed inthe second patrol period, but the present invention is not limited tothis example. For example, the patrol controller portion 50 may operateto complete the dummy read to all the patrol target blocks in the patrolperiod, on the basis of the count of the timer 24 and the remaining timeof the patrol period. In this case, when the remaining time of thepatrol period shortens, the patrol controller portion 50 performsinterruption processing to the operation based on the command from thehost apparatus 2, and preferentially executes the dummy read based onthe patrol operation.

Furthermore, there has been described above the example where the dummyread is executed to each patrol target block once in the patrol period,but the present invention is not limited to this example. For example,the number of times of dummy read to be executed in each patrol periodmay be changed on the basis of the priority. Description is made as tothe present example with reference to FIG. 23. FIG. 23 shows a modifiedexample of the patrol operation based on the priority in the fourthembodiment.

As shown in FIG. 23, the patrol controller portion 50 executes the dummyread to the block BLK of a high priority plural times in the patrolperiod on the basis of the priority of the patrol target block which isdetermined by the priority decision portion 52. Specifically, forexample, the patrol controller portion 50 executes the dummy read to thepatrol target block of the high priority three times, executes the dummyread to the patrol target block of the medium priority twice, andexecutes the dummy read to the patrol target block of the low priorityonce in the patrol period. Then, for example, the patrol controllerportion 50 executes the dummy read in the order of the high priority,the medium priority, the low priority, the high priority, the mediumpriority and the high priority in the patrol period. In this way, thepatrol controller portion 50 initially executes the dummy read to thepatrol target blocks of the respective priorities in the patrol period,and executes the initial dummy read to the patrol target block of themedium priority or the low priority in the first half of the patrolperiod.

It is to be noted that in a case where the patrol controller portion 50executes the dummy read to the same block BLK plural times in the patrolperiod on the basis of the priority, the processing order for dummy readis not limited to the above-mentioned order. In this case, the patrolcontroller portion 50 may employ any order as the processing order fordummy read.

Furthermore, there has been described above the example where in thepatrol period, the patrol controller portion 50 executes the dummy readto the patrol target block having the high priority plural times, andexecutes the dummy read to the patrol target block having the lowpriority once, but the present invention is not limited to this example.For example, the number of the times of the dummy read to the patroltarget block with each priority may be set to any number, and the dummyread may be executed to the patrol target block of the low priorityplural times.

[4-3] Effect of Fourth Embodiment

According to the memory system 1 of the above-mentioned fourthembodiment, it is possible to preferentially execute the dummy read tothe block BLK of high importance. Hereinafter, description will be madeas to a detailed effect of the memory system 1 according to the fourthembodiment.

For example, the patrol target blocks include the block BLK to storeuser data, and the block BLK to store the debug information or the likefor management of the memory system 1 by the memory controller 20, andeven two regions both to store user data occasionally have differentaccess frequencies depending on a type of user data to be stored.Furthermore, in the memory cell transistor MT, there is the tendencythat as the bit data being stored in one memory cell transistor MTincreases, possibility of occurrence of the read error increases in thefirst state of the memory cell transistor MT.

In other words, according to the memory system 1, the patrol targetblocks occasionally have different importance degrees and effects in theexecution of the dummy read. For example, the dummy read in the blockBLK of the high access frequency is more important than the dummy readin the block BLK of the low access frequency. Furthermore, the dummyread in the block BLK to which the MLC mode is applied as the write modehas a larger effect of inhibiting the occurrence of the read error thanthe dummy read in the block BLK to which the SLC mode is applied.

Consequently, in the memory system 1 according to the fourth embodiment,the priority of the dummy read to the patrol target block is set on thebasis of the importance and effect of the dummy read. Specifically, thepriority decision portion 52 determines the priority to each patroltarget block with reference to the attribute table 60 including variouspieces of information of the block BLK. Then, the patrol controllerportion 50 executes the patrol operation on the basis of the prioritydetermined by the priority decision portion 52. That is, the patrolcontroller portion 50 preferentially executes the dummy read to theblock BLK in which the importance and effect of the dummy read are high.

In consequence, according to the memory system 1 of the fourthembodiment, in each patrol period, the memory cell transistor MT in theblock BLK in which the importance and effect of the dummy read are highcan be maintained in the second state. That is, in the memory system 1according to the fourth embodiment, it is possible to minimize theinfluence even in a case the dummy read to all the patrol target blocksis not completed in the patrol period. Therefore, in the memory system 1according to the fourth embodiment, it is possible to minimize drop ofan operation speed of the memory system 1.

It is to be noted that in the memory system 1 according to the fourthembodiment, the dummy read may be executed to the same block BLK pluraltimes in each patrol period on the basis of the priority determined bythe priority decision portion 52. Consequently, in the memory system 1according to the fourth embodiment, in a case where the blocks BLKs aredifferent from each other in the time necessary for the memory celltransistor MT to transition from the second state to the first state,the dummy read may be executed to each patrol target block at the mostsuitable interval.

Furthermore, in the memory system 1 according to the fourth embodiment,the priority may be set on the basis of the structure of the NAND-typeflash memory 10. In this case, the priority decision portion 52 raisesthe priority of the block which is easily transitions from the firststate to the second state due to its physical structure, e.g., the blockwhich is close to a chip end, or the like.

Additionally, in the memory system 1 according to the fourth embodiment,the priority may be set on the basis of hint information acquired fromthe host apparatus 2. In this case, the priority decision portion 52raises the priorities of the block BLK including a logical block addresswhich is frequently accessed, and the block BLK including a logicalblock address into which important data is stored. Furthermore, thepriority decision portion 52 may lower the priority of the logical blockaddress which is not included in the hint information. The presentinvention is not limited to this example, and the priority decisionportion 52 may lower the priority of the block BLK included in namespacewhich is not used, with reference to information for managing thelogical address space as multiple subspaces (e.g., namespaces).

In addition, according to the memory system 1 of the fourth embodiment,a block of an extremely low priority may be excluded from the patroltarget blocks. In this case, for example, the patrol controller portion50 may provide a predetermined threshold to the priority and exclude,from the patrol target blocks, the patrol target block having thepriority which is lower than this predetermined threshold.

[5] Fifth Embodiment

A fifth embodiment relates to a managing method using flags in a patrolperiod, in a case where blocks BLKs share a control signal of a blockdecoder. Hereinafter, description will be made as to differences of amemory system 1 according to a fifth embodiment from the first throughfourth embodiments.

[5-1] Constitution

FIG. 24 shows detailed example constitution of a memory cell array 11, arow decoder module 13 and a voltage generator 19 in the fifthembodiment, and shows a constitution corresponding to one word line WLi(i is an integer of 0 or more and 7 or less) contained in each block BLKand provided in the same layer. As shown in FIG. 24, in the fifthembodiment, the memory cell array 11 includes memory block groups GRs,the row decoder module 13 includes transistors TRs and a block decoderBD, and the voltage generator 19 includes a CG driver 70.

Each memory block group GR includes, for example, four blocks BLKs. Forexample, the memory block groups GRs include a first memory block groupGR1 and a second memory block group GR2, the first memory block groupGR1 includes blocks BLK0 through BLK3, and the second memory block groupGR2 includes blocks BLK4 through BLK7. It is to be noted that the numberof the blocks BLKs included in each memory block group GR is not limitedto this example, and may be designed to any number.

The transistors TRs are connected to different blocks BLKs,respectively. For example, the transistors TRs include transistors TR0through TR7. One end of each of the transistors TR0 through TR7 isconnected to the word line WLi of each of the blocks BLK0 through BLK7.The other ends of the transistors TR0 through TR3 are connected tosignal lines CG0 through CG3, respectively, and a control signal BS1 isinput into a gate of each of the transistors TR0 through TR3. The otherends of the transistors TR4 through TR7 are connected to the signallines CG0 through CG3, respectively, and a control signal BS2 is inputinto a gate of each of the transistors TR4 through TR7.

The block decoder BD outputs the control signals BS1 and BS2 on thebasis of address information stored in an address register 15B. Thecontrol signals BS1 and BS2 correspond to the memory block groups GR1and GR2, respectively. That is, during various operations, the blockdecoder BD adjusts, to an “H”-level, the control signal BS correspondingto the memory block group GR including the block BLK to be selected, andadjusts the control signal BS corresponding to the other memory blockgroup GR to an “L”-level. It is to be noted that FIG. 24 shows thecontrol signals BS1 and BS2, but the block decoder BD may output acontrol signal BS corresponding to another memory block group GR.

The CG driver 70 may generate a voltage to be supplied to signal linesCG0 through CG3 during various operations. Furthermore, the CG driver 70may generate different voltages for the respective signal lines CGs.During various operations, for example, the CG driver 70 applies anytype of operation voltage (e.g., a read voltage) to the signal line CGcorresponding to the selected block BLK, and applies a ground voltageVSS to the signal line CG corresponding to the non-selected block BLK.

It is to be noted that the constitution concerned with one word line WLicontained in each block BLK has been described above, but another wirecontained in each block BLK has a constitution similar to the aboveconstitution. For example, the row decoder module 13 includestransistors TR0, and one end of each of the different transistors TR0 isconnected to each of word lines WL0 through WL7 contained in a blockBLK0. Then, the control signal BS1 is input into gates of thesetransistors TR0, and the other ends of the transistors TR0 are connectedto different signal lines CG0, respectively. The rest of constitution ofthe memory system 1 according to the fifth embodiment is similar to theconstitution of the memory system 1 according to the first embodiment,and hence, description is omitted.

[5-2] Operation

FIG. 25 is a flow chart showing an example of a patrol operation in thememory system 1 according to the fifth embodiment. The flow chart isdifferent from the flow chart described in the first embodiment withreference to FIG. 7 in that the processing of the step S12 is omittedand processing of steps S50 and S51 is inserted after the processing ofstep S11. It is to be noted that in the present operation, a patrolcontroller portion 50 manages a PATROLLED flag. The PATROLLED flag isgiven to each block, and is a flag indicating whether or not dummy readhas already been executed (or, the dummy read operation is required).The PATROLLED flag is held, for example, in an internal memory 22, andin the patrol period, a block BLK to which “0 (a reset state)” is givenindicates the block before the dummy read, and a block BLK to which “1(a set state)” is given indicates the block after the dummy read orindicates that the dummy read is not required.

In the step S11, a processor 21 executes an operation based on a commandfrom a host apparatus 2. For example, the processor 21 executes an eraseoperation, when receiving a command to execute garbage collection fromthe host apparatus 2 in step S10.

Next, in the step S11, the processor 21 determines whether or not theerase operation is executed (the step S50). When the erase operation isnot executed (NO in the step S50), the processor 21 proceeds to stepS13. The patrol controller portion 50 sets the PATROLLED flag of theblock BLK subjected to the dummy read to “1”, when the dummy read isexecuted in the step S13. Furthermore, when the erase operation isexecuted in the step S11 (YES in the step S50), the patrol controllerportion 50 updates the PATROLLED flag in the patrol period (the stepS51).

Specifically, the patrol controller portion 50 resets, to “0”, thePATROLLED flag of the block other than the block BLK that is an erasetarget in a group of blocks BLKs included in the memory block group GRincluding the block BLK that is the erase target in the immediatelypreceding step S11. It is to be noted that when the blocks BLKs areerased blocks BLKs and do not hold any valid data, the PATROLLED flagmay be maintained at “1”.

The block BLK in which the PATROLLED flag is reset in the step S51becomes a target for the dummy read again, even when the dummy read isexecuted to the block in the patrol period. Then, the block BLK in whichthe PATROLLED flag is reset is selected as the target for the dummyread, for example, in the next step S13. The present invention is notlimited to this example, and the patrol controller portion 50 mayexecute the dummy read to the block BLK in which the PATROLLED flag isreset as soon as possible after the PATROLLED flag is reset.

It is to be noted that there has been described above the example wherethe processor 21 executes the erase operation on the basis of thecommand to execute the garbage collection from the host apparatus 2, butthe present invention is not limited to this example. For example, evenwhen the processor 21 executes an erase operation based on a garbagecollection operation irrespective of the command from the host apparatus2, the processor may proceed to the operation of the step S51 bydetermining, in the step S50, whether or not the erase operation isexecuted. Operations in the rest of steps shown in FIG. 25 is similar tothe operation described in the first embodiment, and hence, descriptionis omitted.

FIG. 26 shows an example of the patrol operation described above. FIG.26 shows the example of the patrol operation to be applied to theconstitution of the memory cell array 11 in the fifth embodiment, andshows states of the PATROLLED flags before and after the erase operationin the first memory block group GR1 and the second memory block groupGR2.

As shown in FIG. 26, before the erase operation, the PATROLLED flags ofthe blocks BLK0 and BLK1 of the memory block group GR1 are “1”, and thePATROLLED flags of the blocks BLK2 and BLK3 are “0”. Furthermore, thePATROLLED flags of the blocks BLK4 to BLK7 of the memory block group GR2are “1”. Then, in the present example, the erase operation to the blockBLK2 is executed in this state.

After the erase operation, “1” is initially set to the PATROLLED flag ofthe block BLK2 of the erase target. This is because there is no data tobe targeted for reading in the block BLK2 after the erase operation.Then, the PATROLLED flags of the other blocks BLK0 and BLK1 in thememory block group GR including the block BLK2 of the erase target arereset to “0”. It is to be noted that when the PATROLLED flag indicates“0” in the memory block group, the PATROLLED flag is still maintained at“0”. Furthermore, as for the blocks BLKs included in other memory groupGR, the PATROLLED flag is not updated.

Next, description will be made as to a waveform when a first dummy readand a second dummy read are executed in a NAND-type flash memory 10 ofthe fifth embodiment, with reference to FIG. 27 and FIG. 28. Each ofFIG. 27 and FIG. 28 shows an example of each of a command sequence and awaveform in each of the first dummy read and the second dummy read. Thefirst dummy read and the second dummy read are different from thosedescribed in the first embodiment with reference to FIG. 9 and FIG. 10,in waveform of the word line WL corresponding to each signal line CG.

For example, when the block BLK0 corresponding to the signal line CG0 isselected in the first dummy read shown in FIG. 27, a waveform of theword line WL connected to each signal line CG0 is similar to thewaveform of the word line WL in FIG. 9. On the other hand, for example,the word line WL connected to each of the signal lines CG1 to CG3corresponding to the non-selected block BLK is maintained at a groundvoltage VSS in the first dummy read. The rest of operation of the firstdummy read in the fifth embodiment is similar to the operation of thefirst dummy read described in the first embodiment with reference toFIG. 9, and hence, description is omitted.

For example, when the block BLK0 corresponding to the signal line CG0 isselected in the second dummy read shown in FIG. 28, a waveform of theword line WL connected to each signal line CG0 is similar to thewaveform of the word line WL in FIG. 10. On the other hand, for example,the word line WL connected to each of the signal lines CG1 to CG3corresponding to the non-selected block BLK is maintained at the groundvoltage VSS in the second dummy read. The rest of operation of thesecond dummy read in the fifth embodiment is similar to the operation ofthe second dummy read described in the first embodiment with referenceto FIG. 10, and hence, description is omitted.

It is to be noted that there has been described above the example wherethe PATROLLED flag is updated on the basis of the erase operation to theblock BLK in the memory block group GR, but the present invention is notlimited to this example. For example, the processor 21 may set “1” tothe PATROLLED flag in the block BLK in which a read operation or a writeoperation is executed, when the read operation or the write operation isexecuted on the basis of the command from the host apparatus 2. This isbecause an effect similar to the effect of the dummy read can beexpected in the read operation, and a verifying read operation in thewrite operation.

Furthermore, for example, the processor 21 may update the PATROLLED flagin the memory block group GR on the basis of the number of times of theerase operation, the read operation and the write operation included inthe memory block group GR. Description will be made as to the presentexample with reference to FIG. 29. FIG. 29 is a flow chart showing anexample of an operation in a memory system 1 according to a modifiedexample of the fifth embodiment. The flow chart is different from theflow chart described in the first embodiment with reference to FIG. 7 inthat the processing of the step S12 is omitted, processing of step S52is inserted before the processing of the step S10, and processing ofsteps S53 through S56 is inserted after the processing of the step S11.

As shown in FIG. 29, when the patrol period starts, the patrolcontroller portion 50 initially resets a counter to a specified value(the step S52). This counter is associated with each block BLK, andheld, for example, in the internal memory 22. Furthermore, the specifiedvalue of the counter may be set to any value. Hereinafter, descriptionwill be made as to an example where the specified value of the counteris 1000.

After the step S52, the processor 21 executes the processing of thesteps S10 and S11. Then, after the step S11, the patrol controllerportion 50 executes count processing (the step S53). Specifically, whenthe read operation, the write operation or the erase operation isexecuted in the processing of the step S11, the patrol controllerportion 50 initially resets the counter with the selected block BLK tothe specified value and sets the PATROLLED flag of the selected blockBLK to “1”. The reason why the counter is reset to the specified valueis similar to the reason why the PATROLLED flag is set to “1”.Specifically, an effect similar to the effect of the dummy read can beexpected in each of the read operation and the verifying read operationin the write operation, and there is no data to be targeted for readingafter the erase operation.

Then, in a memory block group GR of the selected block BLK, the patrolcontroller portion 50 performs decreasing the counters associated withthe rest of the blocks BLKs in the memory block group GR (hereinafterreferred to as the block(s) in the common group) on the basis of theoperation executed in the selected block BLK in the step S11.

For example, when one erase operation (in a block BLK unit) is executedin the selected block BLK, the patrol controller portion 50 subtracts1000 from a value of the counter with the block BLK of the common group.When one write operation (in a word line WL unit) is executed in theselected block BLK, the patrol controller portion 50 subtracts 10 fromthe value of the counter with the block BLK of the common group. Whenone read operation is executed, the patrol controller portion 50subtracts 1 from the value of the counter with the block BLK of thecommon group. It is to be noted that the value to be subtracted from thevalue of the counter by the patrol controller portion 50 on the basis ofvarious operations is merely an example, and any value may be set.

Next, the patrol controller portion 50 determines whether there is theblock BLK with which the counter underflows (the step S54). When thereis no block BLK with which the counter underflows (NO in the step S54),the patrol controller portion 50 proceeds to processing of step S13.When there is a block BLK with which the counter underflows (YES in thestep S54), the patrol controller portion 50 resets, to “0”, thePATROLLED flag of the block BLK with which the counter underflows (thestep S55), and sets the block as the target for the dummy read again.

Then, when the dummy read is executed in the step S13, the patrolcontroller portion 50 resets, to the specified value, the counter withthe block BLK subjected to the dummy read, and sets the PATROLLED flagto “1” (the step S56). It is to be noted that, for example, the blockBLK in which the PATROLLED flag is reset is the target for the dummyread in the step S13 to be executed next. Operations in the rest of thesteps shown in FIG. 29 is similar to the operation described in thefirst embodiment, and hence, description is omitted.

Additionally, there has been described above the example where, when thewrite operation is executed in the processing of the step S11, thepatrol controller portion 50 resets the counter with the selected blockBLK to the specified value and sets the PATROLLED flag of the selectedblock BLK to “1” in the step S53, but the present invention is notlimited to this example. For example, the write operation executed inthe processing of the step S11 is occasionally a write operationperformed without executing a verifying operation after a program pulseis last applied. In this case, for example, the patrol controllerportion 50 may set the counter with the block to underflow to 0 or less,and reset the PATROLLED flag to “0”. This is because a memory celltransistor MT in the block BLK is in a first state, when the writeoperation ends in a state where the program pulse is last applied.

[5-3] Effect of Fifth Embodiment

According to the memory system 1 of the above-mentioned fifthembodiment, it is possible to inhibit drop of an operation speed.Hereinafter, description will be made as to a detailed effect of thememory system 1 according to the fifth embodiment.

For example, in a case where the NAND-type flash memory 10 has such aconstitution as shown in FIG. 24 and the read operation, the writeoperation, the erase operation or the like is executed to a certainblock BLK in the memory block group GR, a threshold voltage of thememory cell transistor MT included in each block BLK of the group GRoccasionally fluctuates. This fluctuation of the threshold voltage iscaused by a change of the state of the memory cell transistor MT due tothe voltage applied to the memory cell transistor MT in the same manneras in the creep up phenomenon described in the first embodiment.

To solve such a problem, in the memory system 1 according to the fifthembodiment, the patrol controller portion 50 resets the PATROLLED flagof the block BLK included in the memory block group GR, when the eraseoperation is executed in the certain block BLK of the memory block groupGR. That is, the patrol controller portion 50 also resets the PATROLLEDflag of the block BLK subjected to the dummy read, to set the block asthe target for the dummy read in the patrol period again.

Consequently, in the memory system 1 according to the fifth embodiment,the memory cell transistor MT changed from a second state by the eraseoperation can transition to the second state again. Therefore, in thememory system 1 according to the fifth embodiment, it is possible tosuppress read errors due to the fluctuation of the threshold voltagewhich is caused by the erase operation, and hence, it is possible toinhibit the drop of the operation speed of the memory system 1.

[6] Sixth Embodiment

In a memory system 1 according to a sixth embodiment, the number ofblocks to be selected during a second dummy read is set on the basis ofpower consumption information received from a host apparatus 2.Hereinafter, description will be made as to differences of the memorysystem 1 according to the sixth embodiment from the first through fifthembodiments.

[6-1] Constitution

FIG. 30 shows detailed example constitution of the host apparatus 2 anda processor 21 in a case where the number of the blocks to be selectedduring the second dummy read is set on the basis of the powerconsumption information. As shown in FIG. 30, in the sixth embodiment,the host apparatus 2 stores power consumption information 61, and theprocessor 21 further functions as a partition setting portion 53.

The power consumption information 61 is information obtained byestimating power consumption of the memory system 1, and is setbeforehand, for example, on the basis of a combination of the hostapparatus 2 and the memory system 1, a performance of the memory system1, a standard of a host interface circuit 23, or the like. Then, thepower consumption information 61 is transmitted to the memory system 1,for example, at a startup time of the memory system 1.

The partition setting portion 53 sets block partition (or blockgrouping) on the basis of the power consumption information 61 receivedvia the host interface circuit 23. Specifically, the partition settingportion 53 changes the number of the partitions obtained by dividing amemory cell array 11 of a NAND-type flash memory 10, on the basis of thepower consumption information 61, and assigns a partition ID to aphysical block address of each block BLK. FIG. 31 shows an example wherethe memory cell array 11 includes 1024 blocks BLKs and the 1024 blocksare divided into 16 partitions. FIG. 31 is a table showing an example ofa relation between partition IDs and physical block addresses in thememory system 1.

In a case where 1024 blocks BLKs are divided into 16 partitions, thenumber of the blocks BLKs contained in one partition is 64, and hence,as shown in FIG. 31, a partition ID “1” is assigned to physical blockaddresses “0” through “63”, and a partition ID “2” is assigned tophysical block addresses “64” through “127”. Afterward, the partitionIDs are also similarly assigned to the physical block addresses.

[6-2] Operation

FIG. 32 is a flow chart showing an example of a patrol operation in thememory system 1 according to the sixth embodiment, and shows anoperation example of the memory system 1 in the case of setting thepartitions based on the power consumption information 61.

As shown in FIG. 32, the memory system 1 starts up on the basis of anoperation by the host apparatus 2, an operation by a user, or the like(step S60). At the startup time of the memory system 1, the hostapparatus 2 transmits the power consumption information 61 to the memorysystem 1, and the memory system 1 receives the power consumptioninformation 61 (step S61). Specifically, the power consumptioninformation 61 transmitted by the host apparatus 2 is stored, forexample, in an internal memory 22 via the host interface circuit 23. Itis to be noted that a storage area in which the power consumptioninformation 61 is stored is not limited to this example, and may be, forexample, the DRAM 3.

Next, the partition setting portion 53 sets the partitions on the basisof the received power consumption information 61 (step S62). FIG. 33shows examples of the setting of the partitions and a relation betweenthe number of selected blocks and the power consumption when the seconddummy read is executed.

As shown in FIG. 33, for example, in a case where the partition settingportion 53 divides 1024 blocks BLKs into 128, 64, 32, or 16 partitions,the number of the selected blocks during the second dummy read is 8, 16,32, or 64, respectively. In the second dummy read, as the number of theblocks BLKs to be selected increases, a charging time of the word lineWL lengthens. Therefore, the power consumption increases. To solve sucha problem, the partition setting portion 53 selects the small number ofthe partitions to increase the number of the blocks to be simultaneouslyselected (i.e., activated at once), with reference to the powerconsumption information 61 and the information shown in FIG. 33 in thestep S62, in a case where the memory system 1 allows a large powerconsumption. On the other hand, in a case where the memory system 1 onlyallows only a small power consumption, the partition setting portion 53selects the large number of the partitions to decrease the number of theblocks to be simultaneously selected. That is, the partition settingportion 53 sets the partitions so that the power consumption in the caseof selecting the number of blocks BLKs in a unit of partition during thesecond dummy read falls in budget of the power consumption in the memorysystem 1. A table including information concerning the partitions set atthis time may be stored in the internal memory 22 or the DRAM 3.

Next, for example, a patrol controller portion 50 executes the patroloperation of the steps S10 through S14 described in the first embodimentwith reference to FIG. 7. Then, a patrol controller portion 50designates the set partitions, when the second dummy read is executed inthe step S13. Then, a sequencer 17 of the NAND-type flash memory 10selects the partition, to execute the second dummy read to the block BLKincluded in the partition. That is, the sequencer 17 executes the seconddummy read in the unit of partition.

It is to be noted that there has been described above the example wherethe processing of the steps S10 through S14 is executed after theprocessing of the step 62, but the present invention is not limited tothis example. For example, after the processing of the step S62, anyoperation described in the first through fifth embodiments isapplicable.

[6-3] Effect of Sixth Embodiment

As described above, in the memory system 1 according to the sixthembodiment, the partitions are set on the basis of a usable powerconsumption of the memory system 1, and the second dummy read isexecuted in the unit of partition during the patrol operation.

Consequently, in the memory system 1 according to the sixth embodiment,it is possible to execute the second dummy read to the number of theselected blocks which is most suitable for the budget of the powerconsumption of the memory system 1. Furthermore, in the memory system 1according to the sixth embodiment, the patrol operation can be executedwithout exceeding the budget of the power consumption, and hence, astable operation can be performed.

Furthermore, in the memory system 1 according to the sixth embodiment,it is possible to execute the second dummy read to the blocks BLK of allpatrol targets at the startup time of the memory system 1. Consequently,in the memory system 1 according to the sixth embodiment, it is possibleto cause a memory cell transistor MT to transition from a first state toa second state in early stages after the startup of the memory system 1.Therefore, in the memory system 1 according to the sixth embodiment, itis possible to suppress deterioration of latency during a read operationafter the startup of the memory system 1, and it is possible to inhibitdrop of an operation speed.

[7] Seventh Embodiment

A memory system 1 according to a seventh embodiment is different fromthe memory system 1 according to the sixth embodiment in that aprocessing order for a dummy read operation (may be simply referred toas a dummy read order) is set on the basis of priority informationreceived from a host apparatus 2. Hereinafter, description will be madeas to differences of the memory system 1 according to the seventhembodiment from the first through sixth embodiments.

[7-1] Constitution

FIG. 34 shows detailed example constitution of the host apparatus 2 andthe memory system 1 in a seventh embodiment. As shown in FIG. 34,according to the seventh embodiment, the host apparatus 2 further storespriority information 62, and a priority decision portion 52 described inthe fourth embodiment with reference to FIG. 20 further has a differentfunction.

The priority information 62 includes information of a logical blockaddress LBA corresponding to a block BLK to which a dummy read is to bepreferentially executed, in an initial patrol operation after startup ofthe memory system 1. Then, the priority information 62 is transmittedfrom the host apparatus 2 to the memory system 1, for example, at astartup time of the memory system 1. It is to be noted that the hostapparatus 2 may store multiple pieces of priority information 62, andtransmit the multiple pieces of priority information to the memorysystem 1. In a case where the multiple pieces of priority information 62are transmitted to the memory system 1, a priority order of each pieceof priority information 62 may beforehand be determined, or the prioritydecision portion 52 may determine the priority order of each of themultiple pieces of priority information 62 on the basis of the order ofthe multiple pieces of information transmitted to the memory system 1.

The priority decision portion 52 determines a patrol priority on thebasis of the priority information 62 received via a host interfacecircuit 23. This patrol priority is for use in the decision of aprocessing order for the dummy read in the initial patrol operationafter the startup of the memory system 1. Then, a patrol controllerportion 50 executes the initial patrol operation in the processing orderfor the dummy read based on the priority determined by the prioritydecision portion 52. The rest of constitution of the memory system 1according to the seventh embodiment is similar to the constitution ofthe memory system 1 according to the sixth embodiment, and hence,description is omitted.

[7-2] Operation

FIG. 35 is a flow chart showing an example of the patrol operation inthe memory system 1 according to the seventh embodiment, and shows anoperation example of the memory system 1 in a case where the processingorder for the dummy read is determined on the basis of the priorityinformation 62 in the patrol operation.

As shown in FIG. 35, the memory system 1 starts up on the basis of anoperation by the host apparatus 2, an operation by a user, or the like(step S70). At the startup time of the memory system 1, the hostapparatus 2 transmits the priority information 62 to the memory system1, and the memory system 1 receives the priority information 62 (stepS71). For example, the priority information 62 transmitted by the hostapparatus 2 is stored in an internal memory 22 via the host interfacecircuit 23. It is to be noted that a storage area in which the priorityinformation 62 is stored is not limited to this example. The DRAM 3 maystore the priority information 62.

Next, the priority decision portion 52 determines the patrol priority onthe basis of the received priority information 62 (step S72). Then, forexample, the patrol controller portion 50 executes the patrol operationof the steps S10 through S14 described in the first embodiment withreference to FIG. 7 in the processing order for the dummy read based onthe patrol priority.

Here, description will be made as to an operation example where thememory system 1 receives first priority information and second priorityinformation in the step S71, with reference to FIG. 36 through FIG. 39.FIG. 36 and FIG. 37 show examples of information based on the firstpriority information and the second priority information, respectively,and FIG. 38 and FIG. 39 show examples of methods of setting the patrolpriorities based on the first priority information and the secondpriority information, respectively.

In the present example, different logical block addresses LBAs aredesignated in the first priority information and the second priorityinformation, respectively, and a priority order of the first priorityinformation is set to be higher than a priority order of the secondpriority information. Furthermore, in the present embodiment, there is adescribed example where the partition setting portion 53 described inthe sixth embodiment divides 1024 blocks BLKs into 16 partitions. Inthis case, for example, physical block addresses PBAs corresponding to apartition ID “1” are “0 through 63”, and physical block addresses PBAscorresponding to a partition ID “2” are “64 through 127”. Afterward, thepartitions are similarly set, and physical block addresses PBAscorresponding to a partition ID “16” are “960 through 1023”.

As shown in FIG. 36 and FIG. 37, the priority decision portion 52associates the physical block address PBA with the logical block addressLBA designated by the first priority information and the second priorityinformation, and further associates the partition IDs corresponding tothe physical block addresses PBAs. For example, a look up table (LUT) isused in associating the logical block address LBA with the physicalblock address PBA.

As shown in FIG. 36, the first priority information designates logicalblock addresses LBAs “11” through “20”. For example, the logical blockaddresses LBAs “11” and “12” are associated with physical blockaddresses PBAs “1012” and “1013”, respectively, and hence, the addressescorrespond to partition ID “16”. The logical block addresses LBAs “13”and “14” are associated with physical block addresses PBAs “64” and“65”, respectively, and hence, the addresses correspond to partition ID“2”. Afterward, the priority decision portion 52 similarly associatesthe logical block address LBA and the physical block address PBA withthe partition ID on the basis of the first priority information.

As shown in FIG. 37, the second priority information designates logicalblock addresses LBAs “100” through “109”. For example, the logical blockaddresses LBAs “100” through “104” are associated with physical blockaddresses PBAs “200” through “204”, respectively, and hence, theaddresses correspond to partition ID “4”. Afterward, the prioritydecision portion 52 similarly associates the logical block address LBAand the physical block address PBA with the partition ID on the basis ofthe second priority information.

Then, the priority decision portion 52 initially determines theprocessing order for the dummy read operation on the basis of the firstpriority information. Specifically, as shown in FIG. 38, the prioritydecision portion 52 calculates the patrol priority for each partition.The patrol priority indicates the number of the physical block addressesPBAs corresponding to the logical block addresses LBAs designated by thepriority information, in each partition. For example, it is indicatedthat the partition with patrol priority value “0” does not include thephysical block address PBA corresponding to the logical block addressLBA designated by the priority information, and the partition isexcluded from patrol operation targets. On the other hand, it isindicated that the partition with a patrol priority value larger than“0” includes the physical block address corresponding to the logicalblock address LBA designated by the priority information, and thepartition is the patrol operation target.

As shown in FIG. 38, for example, the partition ID “1” includes twophysical block addresses PBAs corresponding to the logical blockaddresses LBAs designated by the first priority information shown inFIG. 36. At this time, the priority decision portion 52 determines thatthe patrol priority of the partition ID “1” is “2”. The partition ID “2”includes four physical block addresses PBAs corresponding to the logicalblock addresses LBAs designated by the first priority information, andhence, the priority decision portion 52 determines that the patrolpriority of the partition ID “2” is “4”. Afterward, the prioritydecision portion 52 similarly calculates patrol priority valuescorresponding to other partitions.

Next, the patrol controller portion 50 executes the patrol operation onthe basis of the first priority information. Specifically, the patrolcontroller portion 50 executes the second dummy read to the partitionwith the patrol priority value larger than “0” in a unit of partition.Then, the patrol controller portion 50 updates a PATROLLED flag of thepartition subjected to the second dummy read from “0” (before the dummyread) to “1” (after the dummy read). It is to be noted that the patrolcontroller portion 50 may determine the order of the execution of thesecond dummy read based on the first priority information, on the basisof a value of the patrol priority. For example, the patrol controllerportion 50 executes the second dummy read to the partitions in order ofpatrol priority from higher to lower (e.g., from smaller patrol priorityvalue to larger patrol priority value).

Next, the priority decision portion 52 determines the processing orderfor the dummy read operation on the basis of the second priorityinformation. As shown in FIG. 39, for example, partition ID “2” includesthree physical block addresses PBAs corresponding to the logical blockaddresses LBAs designated by the second priority information shown inFIG. 37, and hence, the priority decision portion 52 determines that thepatrol priority of the partition ID “2” is “3”. Partition ID “4”includes five physical block addresses PBAs corresponding to the logicalblock addresses LBAs designated by the second priority information, andhence, the priority decision portion 52 determines that the patrolpriority of the partition ID “4” is “5”. Afterward, the prioritydecision portion 52 similarly calculates patrol priority valuescorresponding to other partitions.

Then, the patrol controller portion 50 executes the patrol operation onthe basis of the second priority information. Specifically, the patrolcontroller portion 50 executes the second dummy read to the partitionwith the patrol priority value larger than “0” and the PATROLLED flag of“0” in the unit of partition. Then, the patrol controller portion 50updates the PATROLLED flag of the partition subjected to the seconddummy read from “0” (before the dummy read) to “1” (after the dummyread).

It is to be noted that the patrol controller portion 50 may execute thesecond dummy read to the partitions In order of patrol priority fromhigher to lower, in the patrol operation based on the priorityinformation. In this case, the patrol controller portion 50 executes thesecond dummy read on partitions in the order of patrol priorityassociated with each partition from higher to lower (e.g., in the orderof patrol priority value from larger to smaller).

Furthermore, there has been described above the example where theprocessing order for the dummy read operation is determined on the basisof the second priority information, after the patrol operation based onthe first priority information is executed, but the present invention isnot limited to this example. For example, the priority decision portion52 initially calculates the priority of each partition on the basis ofthe first priority information and the second priority information.Then, the patrol controller portion 50 may execute the second dummy readon the basis of the priority determined by the priority decision portion52.

Furthermore, the patrol controller portion 50 may change a dummy readprocess on the basis of the patrol priority as shown in FIG. 40. FIG. 40shows an example of a method of selecting the dummy read process basedon the first priority information, and shows an example where the firstdummy read is executed when the patrol priority value is less than “3”and the second dummy read is executed when the patrol priority value isnot less than “3”.

As shown in FIG. 40, in the patrol operation based on the first priorityinformation, the patrol controller portion 50 executes the first dummyread to the block BLK corresponding to the partition ID “1” in which thepatrol priority is “2”. This first dummy read may continuously beexecuted until the dummy read to all the blocks BLKs included in thepartition is completed, or the first dummy read may be executed only tothe block BLK corresponding to the physical block address PBA whichcorresponds to the logical block address LBA designated by the firstpriority information. Furthermore, the patrol controller portion 50executes the second dummy read to the block BLK corresponding to thepartition ID“2” in which the patrol priority is “4”. For this seconddummy read, for example, all the blocks BLKs included in the partitionare selected, to execute the second dummy read to the selected blocks.Then, for example, an order similar to the order described withreference through FIG. 36 to FIG. 39 is applied as the processing orderfor the dummy read operation in the present example.

In the operation of the memory system 1 according to the above-mentionedseventh embodiment, there has been described the example where thepriority of the patrol operation is determined on the basis of thepriority information received from the host apparatus 2, but the presentinvention is not limited to this example. For example, the prioritydecision portion 52 may determine the priority for the patrol operationon the basis of an access pattern in the previous (e.g., last) startupof the memory system 1.

Specifically, a processor 21 initially captures the access pattern aftera startup of the memory system 1, and stores data of this accesspattern, for example, in a NAND-type flash memory 10. Then, at the nextstartup time of the memory system 1, the processor 21 reads the data ofthe access pattern from the NAND-type flash memory 10. Then, forexample, in the processing of the step S72 described with reference toFIG. 35, the priority decision portion 52 updates the patrol priority ofeach partition on the basis of read information of the access pattern.The rest of operation is similar to the operation described withreference to FIG. 35, and hence, description is omitted.

It is to be noted that there has been described above the example wherethe processing of the steps S10 through S14 is executed after theprocessing of the step S72, but the present invention is not limited tothis example. For example, any operation described in the first throughfifth embodiments is applicable after the processing of the step S72.Alternatively, the operation described in the seventh embodiment may becombined with the operation described in the sixth embodiment. In thiscase, the processing of the step S62 described in the sixth embodimentwith reference to FIG. 32 is inserted, for example, before or after thestep S72.

Furthermore, there has been described above the example where thelogical block address LBA corresponds to the physical block address PBAon a one-to-one basis, but the present invention is not limited to thisexample. For example, one physical block address PBA may correspond tomultiple logical block addresses LBAs. Also in this case, the prioritydecision portion 52 may calculate the patrol priority value on the basisof the number of the physical block addresses PBAs which correspond tothe logical block addresses LBAs designated by the priority informationand which are included in each partition.

Additionally, there has been described above the example where thepriority decision portion 52 determines the priority of the patroloperation on the basis of the number of the physical block addressesPBAs corresponding to the logical block addresses LBAs designated by thepriority information 62, but the present invention is not limited tothis example. For example, the priority decision portion 52 maydetermine the priority of the patrol operation on the basis of thenumber of the logical block addresses LBAs designated by the priorityinformation 62.

It is to be noted that a timing for the host apparatus 2 to transmit thepriority information 62 is not limited to a timing of the startup of thememory system 1, but may be a timing of a normal operation. “The timingof a normal operation of the memory system 1” corresponds to anoperation state of the memory system 1, for example, after the startupoperation of the memory system 1 has been completed. In other words,“the timing of a normal operation” corresponds to a period when thememory system 1 can execute an operation based on a command from thehost apparatus after the memory system 1 has started up. When thepriority information 62 is received during the normal operation, thememory system 1 refers to this priority information 62, for example, atthe next startup. Alternatively, the memory system 1 may set the patrolpriority for the next startup, when receiving the priority information62 during the normal operation. In this case, at the next startup, thememory system 1 refers to the patrol priority set beforehand during theprevious (e.g., last) operation in terms of power cycle.

[7-3] Effect of Seventh Embodiment

According to the memory system 1 of the above-mentioned seventhembodiment, it is possible to execute the dummy read in order ofimportance from higher to lower after the startup of the memory system1. Hereinafter, description will be made as to a detailed effect of thememory system 1 according to the seventh embodiment.

For example, the data stored in the memory system 1 includes managementdata of the memory system 1, and user data. The management data isinvisible from the host apparatus 2, and includes, for example, the LUT.The user data is accessible by the host apparatus 2, and includes, forexample, a boot record, an OS (operating system) image, applicationdata, and archive data. For example, the management data of the memorysystem 1 is accessed internally earlier than the user data, duringstartup processing of the memory system 1 and the host apparatus 2.Furthermore, the boot sector and OS image of the user data are accessedearlier than the application data or the archive data. In this way, thedata accessed in such an early stage has a high importance, and it ispreferable to cause the memory cell transistor MT of the block BLKincluding the data to transition to the second state as soon aspossible.

Thus, in the memory system 1 according to the seventh embodiment, thepatrol operation after the startup of the memory system 1 is executed onthe basis of the priority information 62 received from the hostapparatus 2. Specifically, the host apparatus 2 transmits, to the memorysystem 1, the priority information 62 in which the blocks BLKs requiredto be accessed in the early stage are designated. For example, thepriority information 62 includes the information of the logical blockaddress LBA corresponding to the block BLK in which the boot record andOS image of a comparatively high importance are stored. Then, the memorysystem 1 updates the patrol priority of each partition on the basis ofthe received priority information 62, and executes the dummy readpartitions in order of priority associated with each partition fromhigher to lower in an initial patrol operation after the startup.

Consequently, in the memory system 1 according to the seventhembodiment, the memory cell transistor MT of the partition including theblock BLK of high importance can be transitioned to the second stateearly during the startup processing of the memory system 1. Therefore,in the memory system 1 according to the seventh embodiment, it ispossible to inhibit deterioration of latency during the read operationafter the startup of the memory system 1, and it is possible to inhibitdrop of an operation speed.

It is to be noted that in the seventh embodiment, there has beendescribed above the example where the priority information 62 designatesthe block BLK in which the patrol priority is to be raised, by using thelogical block address LBA, but the present invention is not limited tothis example. For example, the priority information 62 may designate thelogical block address LBA to raise the patrol priority, by usingnamespace IDs. For example, in a case where the namespace ID whichcorresponds to a namespace including the OS image is designated by thepriority information 62, the patrol operation in the memory system 1 isexecuted for the block BLK corresponding to the namespace including theOS image after the startup, prior to the block BLK corresponding to thenamespace storing the archive data.

It is to be noted that in the memory system 1 according to the seventhembodiment, it is possible to update the patrol priority on the basis ofthe namespace ID designated by the host apparatus 2. For example, thehost apparatus 2 selects and properly uses the data (the OS image, thearchive data or the like) to be stored in each namespace. Then, the hostapparatus 2 instructs the memory system 1 on the namespace to which ahigher priority is to be set for the memory system 1 (e.g., thenamespace in which the OS image is stored) by using the namespace ID.Consequently, in the memory system 1, it is possible to update thepatrol priority to the partition (the physical block address PBA) ineach namespace by using the logical block address LBA which belongs tothe namespace.

[8] Modified Examples

A memory system (For example, 1, FIG. 1) of the embodiment includes asemiconductor memory (For example, 10, FIG. 1) and a controller (Forexample, 20, FIG. 1). The semiconductor memory includes blocks eachcontaining memory cells. The controller is configured to instruct thesemiconductor memory to execute a first operation (For example, a firstdummy read, FIG. 9) and a second operation (For example, a second dummyread, FIG. 10). In the first operation and the second operation, thesemiconductor memory selects at least one of the blocks, and applies atleast one voltage to all memory cells contained in said selected blocks.A number of blocks to which said voltage is applied per unit time in thesecond operation is larger than that in the first operation. Inconsequence, there can be provided the memory system capable ofinhibiting drop of an operation speed.

It is to be noted that in the above embodiments, there has beendescribed the example where the memory controller 20 executes the patroloperation to a NAND-type flash memory 10, but the present invention isnot limited to this example. For example, in a case where the memorysystem 1 comprises the NAND-type flash memory 10, the memory controller20 may execute the patrol operation to each of the NAND-type flashmemory 10. Alternatively, the memory controller 20 may execute thepatrol operation to the NAND-type flash memory 10 in sequential, or mayexecute the patrol operations in parallel in the NAND-type flash memorychips 10.

It is to be noted that any combination of various operations describedin the above embodiments may be executed. For example, a combination ofthe patrol operation described in the first embodiment and the patroloperation described in the third embodiment may be executed. In thiscase, the memory system 1 sets a patrol period on the basis oftemperature information, and suitably changes a patrol processing ratein each patrol period to execute the dummy read.

It is to be noted that in the above embodiment, the voltage to beapplied to the word line WL of the selected block BLK in the seconddummy read may be different from the read pass voltage VREAD for use ina write mode applied to the block BLK. In a case where a creep upphenomenon having about the same degree as in a normal read operation iscaused by the second dummy read, for example, the row decoder module 13may apply, to the word line WL, a voltage in a range of VREAD in the SLCmode to VREAD in the TLC mode. In a case where read disturb caused bythe application of the voltage in the second dummy read is to bedecreased, for example, the row decoder module 13 may apply a voltagelower than VREAD in the SLC mode to the word line WL as long as theeffect of the dummy read is not lost. Consequently, it is possible tosuitably change the setting of the voltage applied to the word line WLof the selected block BLK in the second dummy read.

It is to be noted that in the sixth embodiment, there has been describedthe example where the second dummy read to the blocks BLKs of all thepatrol target blocks is executed at the startup time of the memorysystem 1, but the present invention is not limited to this example. Forexample, the patrol controller portion 50 may execute the first dummyread to the blocks BLKs of all the patrol target blocks at the startuptime of the memory system 1. Also in this case, in the memory system 1,it is possible to inhibit the deterioration of the latency during theread operation after the startup of the memory system 1, and it ispossible to inhibit the drop of the operation speed. Furthermore, in thesixth embodiment, there has been described the example where the firstor second dummy read is executed to the block BLK of the patrol target,but the present invention is not limited to this example. For example,during the startup processing of the memory system 1, the patrolcontroller portion 50 may execute the first or second dummy read to allthe blocks BLKs.

It is to be noted that in the above description, “the blocks BLKs of allthe patrol targets” may be all the patrol target blocks BLKs in thememory system 1, all the blocks BLKs in which an address conversiontable to convert a logical address and a physical address is stored, orall the blocks BLKs including at least one piece of valid user data.Alternatively, for example, the block BLK of a high importance at thestartup time of the memory system 1 may be set to the patrol targetblock BLK at the startup time of the memory system 1. In this way, forexample, the patrol target block BLK at the startup time of the memorysystem 1 may suitably be changed.

It is to be noted that in the present description, “valid user data”means data stored in a block BLK corresponding to a physical blockaddress associated with a logical block address, i.e., the physicalblock address PBA referred to by the address conversion table to convertfrom the logical block address to the physical block address.

It is to be noted that in the seventh embodiment, there has beendescribed the example where the memory system 1 updates the patrolpriority on the basis of the priority information 62 received from thehost apparatus 2, but the present invention is not limited to thisexample. For example, the memory system 1 may update the patrol priorityat a startup time, irrespective of the command from the host apparatus2. Hereinafter, description will be made as to an operation of a memorysystem 1 in the present modified example.

For example, in the memory system 1, it is possible to update the patrolpriority on the basis of the access pattern after the previous (e.g.,last) startup. In this case, for example, in the memory system 1,information concerning the access pattern from the host apparatus 2 in apredetermined period after the startup is stored in the NAND-type flashmemory 10. Then, at the next startup, in the memory system 1, theinformation concerning this access pattern is read from the NAND-typeflash memory 10, and, for example, the patrol priority of the block BLKaccessed early after the previous startup is raised. Alternatively, thememory system 1 may update the patrol priority on the basis of the orderof the blocks BLKs accessed by the host apparatus 2.

Furthermore, in the memory system 1, it is possible to update the patrolpriority on the basis of a type of data stored in each block BLK. Inthis case, in the memory system 1, for example, a priority of the patroloperation in the block BLK in which the management data (especially, theaddress conversion table) is stored is set to be higher than that in theblock BLK in which the user data is stored.

The above-mentioned methods of updating the priority of the patroloperation irrespective of the instruction of the host apparatus 2 may beseparately executed or may be executed together. Consequently, in thememory system 1 according to the present modified example, for example,it is possible to raise the patrol priority of a hidden block BLK whichis required to be accessed internally in an early stage but which cannotbe designated with the priority information 62 by the host apparatus 2.Therefore, according to the memory system 1 of the present modifiedexample, it is possible to further inhibit the deterioration of thelatency during the read operation after the startup of the memory system1, and it is possible to further inhibit the drop of the operationspeed.

It is to be noted that in the above embodiment, there has been describedthe example where the read operation of the SLC mode is applied as thefirst dummy read, but the present invention is not limited to thisexample. For example, in the first dummy read, a read operationcorresponding to an upper page in the MLC mode or a read operationcorresponding to a lower page may be applied. In this way, the readoperation of any system is applicable to the first dummy read.

It is to be noted that the number of the blocks to be simultaneouslyselected (i.e., activated) in the second dummy read described in theabove embodiment may be changed by setting the NAND-type flash memory10. FIG. 41 shows an example of a command sequence of a set feature toperform such setting modification. As shown in FIG. 41, the memorycontroller 20 initially issues a set feature command “EFh”, andtransmits the command to the NAND-type flash memory 10. The command“EFh” is issued to instruct the NAND-type flash memory 10 to change aparameter. Next, the memory controller 20 issues the address informationADD, and transmits the information to the NAND-type flash memory 10.This address information ADD designates an address corresponding to theparameter to be changed. Next, the memory controller 20 outputs settingdata Din to the NAND-type flash memory 10 over several cycles. The dataDin output herein is data corresponding to the parameter to be changed.Then, the sequencer 17 controls the sense amplifier module 12, the rowdecoder module 13, or the like to start the set feature process. Whenthe set feature starts, the parameter setting in the NAND-type flashmemory 10 is updated with the specified data. A period denoted with tSetin the drawing is a period in which this set feature process isperformed. When the set feature process ends, for example, there isapplied setting modification of the number of the blocks to besimultaneously selected in the second dummy read of the NAND-type flashmemory 10.

It is to be noted that in the above embodiment, there has been describedthe example where various operations are executed in software, but thepresent invention is not limited to this example. For example, a part ofprocessing may be achieved with dedicated hardware, or all of theprocessing may be achieved with dedicated hardware. For example, in thepatrol operation, a circuit which functions as the patrol controllerportion 50 may be employed. This also applies to the rest of processing.Such hardware may be contained in the memory controller 20 or externallyconnected.

It is to be noted that in the above embodiment, the waveform of the wordline WL has been described in the first dummy read and the second dummyread, but a waveform of the corresponding signal line CG is also similarto the waveform of the word line WL. That is, the voltage being appliedto the word line WL and a period in which the voltage is applied to theword line WL can roughly be known by observing a voltage of thecorresponding signal line CG. It is to be noted that an influence ofvoltage drop by the transistor TR may appear between the voltage of theword line WL and the voltage of the signal line CG.

It is to be noted that in the above embodiment, there has been describedthe example where the MONOS film is used in each memory cell, but thepresent invention is not limited to this example. For example, also inthe case of using the memory cell in which a floating gate is employed,the read operation and the write operation described in the aboveembodiment are executed, whereby a similar effect is obtainable.

The block BLK is, for example, an erase unit of data in thethree-dimensional semiconductor memory device, but is not limitedthereto. Other erase operations are described in U.S. patent applicationSer. No. 13/235,389 entitled “Nonvolatile semiconductor memory device”filed on Sep. 18, 2011, and in U.S. patent application Ser. No.12/694,690 entitled “Non-volatile semiconductor memory device” filed onJan. 27, 2010. These patent applications are incorporated by referenceherein in their entirety.

It is to be noted that in the present description, “connection”indicates electric connection, and does not exclude, for example,connection via another element. Furthermore, in the present description,“cut-off” indicates that the transistor is in an off state, and does notexclude, for example, a state where a micro current such as a leakcurrent of the transistor flows.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A memory system comprising: a nonvolatile memoryincluding a plurality of blocks, each of the plurality of blocksincluding a plurality of word lines; and a controller configured toinstruct the nonvolatile memory to execute a dummy read operation on afirst group of blocks within a first period, wherein, in the dummy readoperation, at least one block of the first group of blocks is selected,and a voltage higher than a ground voltage is applied to each word lineof the plurality of word lines included in the selected block, and thecontroller is further configured to change, on the basis of a remainingtime of the first period, a rate indicating the number of blocks to beselected per unit time.
 2. The memory system according to claim 1,wherein in the dummy read operation, a memory cell transistor connectedto a word line to which the voltage higher than the ground voltage isapplied turns on.
 3. The memory system according to claim 2, wherein inthe dummy read operation, data stored in the memory cell transistor thatturns on is not output to the controller.
 4. The memory system accordingto claim 1, wherein the controller is further configured to manage anaddress conversion table to convert a logical address associated withdata stored in the nonvolatile memory into a physical address of thenonvolatile memory, and each block of the first group of blocks storesat least one piece of valid user data or the address conversion table.5. The memory system according to claim 4, wherein the controller isconfigured to instruct the nonvolatile memory to execute the dummy readoperation on the first group of blocks at a startup of the memorysystem.
 6. The memory system according to claim 1, wherein the dummyread operation includes a first dummy read operation and a second dummyread operation, and the number of blocks selected in one execution ofthe first dummy read operation is smaller than the number of blocksselected in one execution of the second dummy read operation.
 7. Thememory system according to claim 1, wherein the controller is configuredto determine the first period on the basis of temperature of the memorysystem.
 8. A memory system comprising: a semiconductor memory includinga plurality of blocks, each of the plurality of blocks including aplurality of word lines and a plurality of memory cells, each of theplurality of word lines connecting at least one of the plurality ofmemory cells; and a controller configured to: instruct the semiconductormemory to perform a first operation after a power begins to be suppliedto the memory system and before data is read out from a first block tothe controller, wherein, in the first operation, the semiconductormemory applies a voltage to a first word line of the first block anddoes not output, to the controller, data stored in a memory cellconnected to the first word line; and instruct the semiconductor memoryto perform the first operation again within a first period afterinstructing the semiconductor memory to perform the first operation. 9.The memory system according to claim 8, wherein within the first periodafter the first operation is instructed to the semiconductor memory, thefirst word line is in a first state in which a voltage of the first wordline while the first block is not selected as an access target is higherthan a first voltage.
 10. The memory system according to claim 8,wherein the plurality of memory cells are deployed in three dimensions,and the first word line is located at the outermost of the first block.11. The memory system according to claim 8, wherein the controller isfurther configured to: upon instructing the semiconductor memorypredetermined times to execute one of a read operation, a writeoperation, and an erase operation to a second block, instruct thesemiconductor memory to perform the first operation to a third block,the third block being a block within a group that includes the secondblock, the third block being different from the second block.
 12. Thememory system according to claim 8, wherein the controller is furtherconfigured to instruct the semiconductor memory to perform the firstoperation in a case where reading data from the first word line to thecontroller is required while the first word line is in a second state,the second state being a state in which a voltage of the first word linewhile the first block is not selected as an access target is lower thana second voltage, before instructing the semiconductor memory to readdata from the first word line.
 13. A memory system comprising: anonvolatile memory including a plurality of blocks, each of theplurality of blocks including a plurality of word lines; and acontroller configured to instruct the nonvolatile memory to execute adummy read operation on a first group of blocks within a first period,wherein, in the dummy read operation, at least one block of the firstgroup of blocks is selected, and a voltage higher than a ground voltageis applied to each word line of the plurality of word lines included inthe selected block, and the dummy read operation includes a first dummyread operation and a second dummy read operation, and the number ofblocks selected in one execution of the first dummy read operation issmaller than the number of blocks selected in one execution of thesecond dummy read operation.
 14. The memory system according to claim13, wherein in the dummy read operation, a memory cell transistorconnected to a word line to which the voltage higher than the groundvoltage is applied turns on, and in the dummy read operation, datastored in the memory cell transistor that turns on is not output to thecontroller.
 15. The memory system according to claim 13, wherein thecontroller is further configured to manage an address conversion tableto convert a logical address associated with data stored in thenonvolatile memory into a physical address of the nonvolatile memory,each block of the first group of blocks stores at least one piece ofvalid user data or the address conversion table, and the controller isconfigured to instruct the nonvolatile memory to execute the dummy readoperation on the first group of blocks at a startup of the memorysystem.
 16. The memory system according to claim 13, wherein thecontroller is configured to determine the first period on the basis oftemperature of the memory system.
 17. The memory system according toclaim 13, wherein the controller is further configured to change, on thebasis of a remaining time of the first period, a rate indicating thenumber of blocks to be selected per unit time.
 18. The memory systemaccording to claim 13, wherein a processing time for one execution ofthe first dummy read operation is shorter than a processing time for oneexecution of the second dummy read operation.
 19. The memory systemaccording to claim 18, wherein in the second dummy read operation, twoor more blocks are selected and the voltage higher than the groundvoltage is applied concurrently to each word line of the plurality ofword lines included in the selected blocks.
 20. The memory systemaccording to claim 19, wherein the controller is further configured tochange, on the basis of a remaining time of the first period, a rateindicating the number of blocks to be selected per unit time by changinga ratio of the number of the first dummy read operations to the numberof the second dummy read operations to be executed in the first period.